From: Dmitry Osipenko <digetx@gmail.com>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Viresh Kumar <vireshk@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-tegra <linux-tegra@vger.kernel.org>,
Linux PM <linux-pm@vger.kernel.org>
Subject: Re: [PATCH v7 02/37] soc/tegra: pmc: Implement attach_dev() of power domain drivers
Date: Tue, 10 Aug 2021 02:56:52 +0300 [thread overview]
Message-ID: <6741262b-386b-7635-fd42-ebd4f877fddd@gmail.com> (raw)
In-Reply-To: <CAPDyKFq+ExjbGrN=yUUXPKfN_fGrwY6EAYn9a6VUFFU_VjhC=g@mail.gmail.com>
09.08.2021 17:15, Ulf Hansson пишет:
>> We did that in a previous versions of this series where drivers were
>> calling devm_tegra_core_dev_init_opp_table() helper during the probe to
>> initialize performance state of the domain. Moving OPP state
>> initialization into central place made drivers cleaner by removing the
>> boilerplate code.
> I am not against doing this in a central place, like $subject patch
> suggests. As a matter of fact, it makes perfect sense to me.
>
> However, what I am concerned about, is that you require to use genpd
> internal data structures to do it. I think we should try to avoid
> that.
Alright, what do you think about this:
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index a934c679e6ce..5faed62075e9 100644
--- a/drivers/base/power/domain.c
+++ b/drivers/base/power/domain.c
@@ -2669,12 +2669,37 @@ static int __genpd_dev_pm_attach(struct device *dev, struct device *base_dev,
dev->pm_domain->detach = genpd_dev_pm_detach;
dev->pm_domain->sync = genpd_dev_pm_sync;
+ if (pd->default_performance_state) {
+ unsigned int default_pstate;
+
+ ret = pd->default_performance_state(pd, dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to get default performance state for PM domain %s: %d\n",
+ pd->name, ret);
+ goto out;
+ }
+
+ default_pstate = ret;
+
+ if (power_on) {
+ ret = dev_pm_genpd_set_performance_state(dev, default_pstate);
+ if (ret) {
+ dev_err(dev, "failed to set default performance state %u for PM domain %s: %d\n",
+ default_pstate, pd->name, ret);
+ goto out;
+ }
+ } else {
+ dev_gpd_data(dev)->rpm_pstate = default_pstate;
+ }
+ }
+
if (power_on) {
genpd_lock(pd);
ret = genpd_power_on(pd, 0);
genpd_unlock(pd);
}
+out:
if (ret)
genpd_remove_device(pd, dev);
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 81d1f019fa0c..9efb55f52462 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -518,15 +518,14 @@ static const char * const tegra_emc_compats[] = {
* We retrieve clock rate of the attached device and initialize domain's
* performance state in accordance to the clock rate.
*/
-static int tegra_pmc_pd_attach_dev(struct generic_pm_domain *genpd,
- struct device *dev)
+static int tegra_pmc_genpd_default_perf_state(struct generic_pm_domain *genpd,
+ struct device *dev)
{
- struct generic_pm_domain_data *gpd_data = dev_gpd_data(dev);
struct opp_table *opp_table, *pd_opp_table;
struct generic_pm_domain *core_genpd;
struct dev_pm_opp *opp, *pd_opp;
- unsigned long rate, state;
struct gpd_link *link;
+ unsigned long rate;
struct clk *clk;
u32 hw_version;
int ret;
@@ -633,8 +632,7 @@ static int tegra_pmc_pd_attach_dev(struct generic_pm_domain *genpd,
* RPM-resume of the device. This means that drivers don't need to
* explicitly initialize performance state.
*/
- state = pm_genpd_opp_to_performance_state(&core_genpd->dev, pd_opp);
- gpd_data->rpm_pstate = state;
+ ret = pm_genpd_opp_to_performance_state(&core_genpd->dev, pd_opp);
dev_pm_opp_put(pd_opp);
put_pd_opp_table:
@@ -1383,7 +1381,7 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
pg->id = id;
pg->genpd.name = np->name;
- pg->genpd.attach_dev = tegra_pmc_pd_attach_dev;
+ pg->genpd.default_performance_state = tegra_pmc_genpd_default_perf_state;
pg->genpd.power_off = tegra_genpd_power_off;
pg->genpd.power_on = tegra_genpd_power_on;
pg->pmc = pmc;
@@ -1500,7 +1498,7 @@ static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
return -ENOMEM;
genpd->name = np->name;
- genpd->attach_dev = tegra_pmc_pd_attach_dev;
+ genpd->default_performance_state = tegra_pmc_genpd_default_perf_state;
genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
index 21a0577305ef..cd4867817ca5 100644
--- a/include/linux/pm_domain.h
+++ b/include/linux/pm_domain.h
@@ -143,6 +143,8 @@ struct generic_pm_domain {
struct device *dev);
void (*detach_dev)(struct generic_pm_domain *domain,
struct device *dev);
+ int (*default_performance_state)(struct generic_pm_domain *domain,
+ struct device *dev);
unsigned int flags; /* Bit field of configs for genpd */
struct genpd_power_state *states;
void (*free_states)(struct genpd_power_state *states,
>> I can revert back to the previous variant, although this variant works
>> well too.
> I looked at that code and in that path we end up calling
> dev_pm_opp_set_rate(), after it has initialized the opp table for the
> device.
>
> Rather than doing the OF parsing above to find out the current state
> for the device, why can't you just call dev_pm_opp_set_rate() to
> initialize a proper vote instead?
>
For some devices clock rate is either preset by bootloader, or by clk driver, or by assigned-clocks in a device-tree. And then I don't see what's the difference in comparison to initialization for the current rate.
For some devices, like memory controller, we can't just change the clock rate because it's a complex procedure and some boards will use fixed rate, but the power vote still must be initialized.
next prev parent reply other threads:[~2021-08-09 23:56 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-01 23:26 [PATCH v7 00/37] NVIDIA Tegra power management patches for 5.15 Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 01/37] soc/tegra: pmc: Temporarily disable PMC state syncing Dmitry Osipenko
2021-08-12 16:02 ` Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 02/37] soc/tegra: pmc: Implement attach_dev() of power domain drivers Dmitry Osipenko
2021-08-02 14:48 ` Ulf Hansson
2021-08-02 18:23 ` Dmitry Osipenko
2021-08-04 9:59 ` Ulf Hansson
2021-08-04 21:16 ` Dmitry Osipenko
2021-08-09 14:15 ` Ulf Hansson
2021-08-09 23:56 ` Dmitry Osipenko [this message]
2021-08-10 10:51 ` Ulf Hansson
2021-08-11 19:30 ` Dmitry Osipenko
2021-08-11 22:41 ` Dmitry Osipenko
2021-08-12 1:40 ` Dmitry Osipenko
2021-08-12 11:17 ` Ulf Hansson
2021-08-12 16:24 ` Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 03/37] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 04/37] soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 05/37] dt-bindings: clock: tegra-car: Document new tegra-clocks node Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 06/37] clk: tegra: Support runtime PM and power domain Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 07/37] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2021-07-01 23:26 ` [PATCH v7 08/37] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 09/37] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 10/37] gpu: host1x: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 11/37] gpu: host1x: Add stub driver for MPE, VI, EPP and ISP Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 12/37] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 13/37] drm/tegra: hdmi: Add OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 14/37] drm/tegra: gr2d: Support OPP and power management Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 15/37] drm/tegra: gr3d: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 16/37] drm/tegra: vic: Stop channel before suspending Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 17/37] usb: chipidea: tegra: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 18/37] bus: tegra-gmi: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 19/37] pwm: tegra: Add runtime PM and OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 20/37] mmc: sdhci-tegra: " Dmitry Osipenko
2021-07-02 3:39 ` kernel test robot
2021-07-01 23:27 ` [PATCH v7 21/37] mtd: rawnand: tegra: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 22/37] soc/tegra: fuse: Clear fuse->clk on driver probe failure Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 23/37] soc/tegra: fuse: Add runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 24/37] soc/tegra: fuse: Enable fuse clock on suspend Dmitry Osipenko
2021-07-21 16:00 ` Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 25/37] clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 26/37] spi: tegra20-slink: Improve runtime PM usage Dmitry Osipenko
2021-07-02 8:29 ` kernel test robot
2021-07-01 23:27 ` [PATCH v7 27/37] spi: tegra20-slink: Add OPP support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 28/37] memory: tegra20-emc: Add minimal runtime PM support Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 29/37] memory: tegra30-emc: " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 30/37] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 31/37] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 32/37] media: staging: tegra-vde: Support generic " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 33/37] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 34/37] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 35/37] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 36/37] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko
2021-07-01 23:27 ` [PATCH v7 37/37] soc/tegra: pmc: Enable core domain support on Tegra20 and Tegra30 Dmitry Osipenko
2021-07-09 13:01 ` [PATCH v7 00/37] NVIDIA Tegra power management patches for 5.15 Ulf Hansson
2021-07-09 21:23 ` Dmitry Osipenko
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