From: Dan Lustig <dlustig@nvidia.com>
To: Boqun Feng <boqun.feng@gmail.com>, Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Alan Stern <stern@rowland.harvard.edu>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Peter Anvin <hpa@zytor.com>,
Andrea Parri <parri.andrea@gmail.com>,
Ingo Molnar <mingo@kernel.org>,
"Paul E. McKenney" <paulmck@kernel.org>,
Vince Weaver <vincent.weaver@maine.edu>,
Thomas Gleixner <tglx@linutronix.de>,
Jiri Olsa <jolsa@redhat.com>,
Arnaldo Carvalho de Melo <acme@redhat.com>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
Stephane Eranian <eranian@google.com>,
<linux-tip-commits@vger.kernel.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <mpe@ellerman.id.au>
Subject: Re: [tip:locking/core] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire
Date: Fri, 10 Sep 2021 09:48:55 -0400 [thread overview]
Message-ID: <20a453f3-9b1f-20ab-880b-1018b2e11664@nvidia.com> (raw)
In-Reply-To: <YTstpCYfnL9P1sAA@boqun-archlinux>
On 9/10/2021 6:04 AM, Boqun Feng wrote:
> On Fri, Sep 10, 2021 at 11:33:25AM +0200, Peter Zijlstra wrote:
>> On Fri, Sep 10, 2021 at 08:01:14AM +0800, Boqun Feng wrote:
>>> On Thu, Sep 09, 2021 at 01:03:18PM -0400, Dan Lustig wrote:
>>>> On 9/9/2021 9:35 AM, Will Deacon wrote:
>>>>> On Thu, Sep 09, 2021 at 09:25:30AM +0200, Peter Zijlstra wrote:
>>
>>>>>> The AMOSWAP is a RmW and as such matches the W from the RW->W fence,
>>>>>> similarly it marches the R from the R->RW fence, yielding an:
>>>>>>
>>>>>> RW-> W
>>>>>> RmW
>>>>>> R ->RW
>>>>>>
>>>>>> ordering. It's the stores S and R that can be re-ordered, but not the
>>>>>> sections themselves (same on PowerPC and many others).
>>
>>>> I agree with Will here. If the AMOSWAP above is actually implemented with
>>>> a RISC-V AMO, then the two critical sections will be separated as if RW,RW,
>>>> as Peter described. If instead it's implemented using LR/SC, then RISC-V
>>>
>>> Just out of curiosity, in the following code, can the store S and load L
>>> be reordered?
>>>
>>> WRITE_ONCE(x, 1); // store S
>>> FENCE RW, W
>>> WRITE_ONCE(s.lock, 0); // unlock(s)
>>> AMOSWAP %0, 1, s.lock // lock(s)
>>> FENCE R, RW
>>> r1 = READ_ONCE(y); // load L
>>>
>>> I think they can, because neither "FENCE RW, W" nor "FENCE R, RW" order
>>> them.
>>
>> I'm confused by your argument, per the above quoted section, those
>> fences and the AMO combine into a RW,RW ordering which is (as per the
>> later clarification) multi-copy-atomic, aka smp_mb().
>>
>
> Right, my question is more about the reasoning about why fence rw,w +
> AMO + fence r,rw act as a fence rw,rw.
Is this a RISC-V question? If so, it's as simple as:
1) S and anything earlier are ordered before the AMO by the first fence
2) L and anything later are ordered after the AMO by the second fence
3) 1 + 2 = S and anything earlier are ordered before L or anything later
Since RISC-V is multi-copy atomic, so 1+2 just naturally compose
transitively.
> Another related question, can
> fence rw,w + store + fence w,rw act as a fence rw,rw by the similar
> reasoning? IOW, will the two loads in the following be reordered?
>
> r1 = READ_ONCE(x);
> FENCE RW, W
> WRITE_ONCE(z, 1);
> FENCE W, RW
> r2 = READ_ONCE(y);
>
> again, this is more like a question out of curiosity, not that I find
> this pattern is useful.
Does FENCE W,RW appear in some actual use case? But yes, if it does
appear, this sequence would also act as a FENCE RW,RW on RISC-V.
Dan
> Regards,
> Boqun
>
>> As such, S and L are not allowed to be re-ordered in the given scenario.
>>
>>> Note that the reordering is allowed in LKMM, because unlock-lock
>>> only need to be as strong as RCtso.
>>
>> Risc-V is strictly stronger than required in this instance. Given the
>> current lock implementation. Daniel pointed out that if the atomic op
>> were LL/SC based instead of AMO it would end up being RCtso.
>>
next prev parent reply other threads:[~2021-09-10 13:47 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-26 18:28 [PATCH memory-model 0/5] Updates to the formal memory model Paul E. McKenney
2018-09-26 18:29 ` [PATCH memory-model 1/5] tools/memory-model: Add litmus-test naming scheme Paul E. McKenney
2018-10-02 10:10 ` [tip:locking/core] " tip-bot for Paul E. McKenney
2018-09-26 18:29 ` [PATCH memory-model 2/5] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire Paul E. McKenney
2018-10-02 10:11 ` [tip:locking/core] " tip-bot for Alan Stern
2021-09-08 11:00 ` Peter Zijlstra
2021-09-08 11:44 ` Peter Zijlstra
2021-09-08 14:42 ` Alan Stern
2021-09-08 15:12 ` Peter Zijlstra
2021-09-08 16:08 ` Linus Torvalds
2021-09-09 7:25 ` Peter Zijlstra
2021-09-09 13:35 ` Will Deacon
2021-09-09 17:02 ` Linus Torvalds
2021-09-09 18:59 ` Alan Stern
2021-09-09 17:03 ` Dan Lustig
2021-09-09 18:00 ` Paul E. McKenney
2021-09-10 14:20 ` Boqun Feng
2021-09-10 15:33 ` Palmer Dabbelt
2021-09-10 16:36 ` Alan Stern
2021-09-10 17:12 ` Peter Zijlstra
2021-09-10 17:56 ` Alan Stern
2021-09-10 17:17 ` Peter Zijlstra
2021-09-12 0:26 ` Boqun Feng
2021-09-10 0:01 ` Boqun Feng
2021-09-10 5:37 ` Boqun Feng
2021-09-10 9:33 ` Peter Zijlstra
2021-09-10 10:04 ` Boqun Feng
2021-09-10 13:48 ` Dan Lustig [this message]
2021-09-10 14:15 ` Boqun Feng
2021-09-09 17:46 ` Paul E. McKenney
2021-09-10 11:08 ` Will Deacon
2021-09-17 3:21 ` Nicholas Piggin
2021-09-17 5:31 ` Nicholas Piggin
2021-09-17 14:36 ` Michael Ellerman
2018-09-26 18:29 ` [PATCH memory-model 3/5] tools/memory-model: Fix a README typo Paul E. McKenney
2018-10-02 10:11 ` [tip:locking/core] " tip-bot for SeongJae Park
2018-09-26 18:29 ` [PATCH memory-model 4/5] tools/memory-model: Add more LKMM limitations Paul E. McKenney
2018-10-02 10:12 ` [tip:locking/core] " tip-bot for Paul E. McKenney
2018-09-26 18:29 ` [PATCH memory-model 5/5] doc: Replace smp_cond_acquire() with smp_cond_load_acquire() Paul E. McKenney
2018-10-02 10:12 ` [tip:locking/core] locking/memory-barriers: " tip-bot for Andrea Parri
2018-10-02 8:28 ` [PATCH memory-model 0/5] Updates to the formal memory model Ingo Molnar
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