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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/31] dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness
Date: Thu, 30 Apr 2020 12:51:12 +0100	[thread overview]
Message-ID: <20200430115142.13430-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix descriptor loading from memory wrt host endianness.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200404122718.25111-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx-zdma.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
index 1c45367f3c6..5f4775f6634 100644
--- a/hw/dma/xlnx-zdma.c
+++ b/hw/dma/xlnx-zdma.c
@@ -299,19 +299,22 @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned int basereg, uint64_t addr)
     s->regs[basereg + 1] = addr >> 32;
 }
 
-static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
+static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr,
+                                 XlnxZDMADescr *descr)
 {
     /* ZDMA descriptors must be aligned to their own size.  */
     if (addr % sizeof(XlnxZDMADescr)) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "zdma: unaligned descriptor at %" PRIx64,
                       addr);
-        memset(buf, 0x0, sizeof(XlnxZDMADescr));
+        memset(descr, 0x0, sizeof(XlnxZDMADescr));
         s->error = true;
         return false;
     }
 
-    address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr));
+    descr->addr = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
+    descr->size = address_space_ldl_le(s->dma_as, addr + 8, s->attr, NULL);
+    descr->attr = address_space_ldl_le(s->dma_as, addr + 12, s->attr, NULL);
     return true;
 }
 
@@ -344,7 +347,7 @@ static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
     } else {
         addr = zdma_get_regaddr64(s, basereg);
         addr += sizeof(s->dsc_dst);
-        address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8);
+        next = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
     }
 
     zdma_put_regaddr64(s, basereg, next);
-- 
2.20.1



  reply	other threads:[~2020-04-30 11:53 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30 11:51 [PULL 00/31] target-arm queue Peter Maydell
2020-04-30 11:51 ` Peter Maydell [this message]
2020-04-30 11:51 ` [PULL 02/31] dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness Peter Maydell
2020-04-30 11:51 ` [PULL 03/31] nrf51: Fix last GPIO CNF address Peter Maydell
2020-04-30 11:51 ` [PULL 04/31] bugfix: Use gicr_typer in arm_gicv3_icc_reset Peter Maydell
2020-04-30 11:51 ` [PULL 05/31] Typo: Correct the name of CPU hotplug memory region Peter Maydell
2020-04-30 11:51 ` [PULL 06/31] hw/net: Add Smartfusion2 emac block Peter Maydell
2020-04-30 11:51 ` [PULL 07/31] msf2: Add EMAC block to SmartFusion2 SoC Peter Maydell
2020-04-30 11:51 ` [PULL 08/31] tests/boot_linux_console: Add ethernet test to SmartFusion2 Peter Maydell
2020-04-30 11:51 ` [PULL 09/31] hw/core/clock: introduce clock object Peter Maydell
2020-04-30 14:35   ` Peter Maydell
2020-10-17 11:47   ` Philippe Mathieu-Daudé
2020-10-20 16:06     ` Philippe Mathieu-Daudé
2020-10-20 16:46       ` Peter Maydell
2020-10-20 17:46         ` Philippe Mathieu-Daudé
2020-04-30 11:51 ` [PULL 10/31] hw/core/clock-vmstate: define a vmstate entry for clock state Peter Maydell
2020-04-30 11:51 ` [PULL 11/31] qdev: add clock input&output support to devices Peter Maydell
2020-04-30 11:51 ` [PULL 12/31] qdev-clock: introduce an init array to ease the device construction Peter Maydell
2020-04-30 11:51 ` [PULL 13/31] docs/clocks: add device's clock documentation Peter Maydell
2020-04-30 11:51 ` [PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts Peter Maydell
2020-04-30 11:51 ` [PULL 15/31] hw/char/cadence_uart: add clock support Peter Maydell
2020-04-30 11:51 ` [PULL 16/31] hw/arm/xilinx_zynq: connect uart clocks to slcr Peter Maydell
2020-04-30 11:51 ` [PULL 17/31] qdev-monitor: print the device's clock with info qtree Peter Maydell
2020-04-30 11:51 ` [PULL 18/31] hw/arm: versal: Setup the ADMA with 128bit bus-width Peter Maydell
2020-04-30 11:51 ` [PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors Peter Maydell
2020-04-30 11:51 ` [PULL 20/31] net: cadence_gem: clear RX control descriptor Peter Maydell
2020-04-30 11:51 ` [PULL 21/31] target/arm: Vectorize integer comparison vs zero Peter Maydell
2020-04-30 11:51 ` [PULL 22/31] hw/arm/virt: dt: move creation of /secure-chosen to create_fdt() Peter Maydell
2020-04-30 11:51 ` [PULL 23/31] hw/arm/virt: dt: add kaslr-seed property Peter Maydell
2020-04-30 11:51 ` [PULL 24/31] target/arm: Restrict the Address Translate write operation to TCG accel Peter Maydell
2020-04-30 11:51 ` [PULL 25/31] target/arm: Make cpu_register() available for other files Peter Maydell
2020-04-30 11:51 ` [PULL 26/31] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] Peter Maydell
2020-04-30 14:30   ` Peter Maydell
2020-04-30 11:51 ` [PULL 27/31] target/arm/cpu: Update coding style to make checkpatch.pl happy Peter Maydell
2020-04-30 14:52   ` Philippe Mathieu-Daudé
2020-04-30 11:51 ` [PULL 28/31] device_tree: Allow name wildcards in qemu_fdt_node_path() Peter Maydell
2020-04-30 11:51 ` [PULL 29/31] device_tree: Constify compat " Peter Maydell
2020-04-30 11:51 ` [PULL 30/31] hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102 Peter Maydell
2020-04-30 11:51 ` [PULL 31/31] hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes Peter Maydell
2020-05-01  2:05 ` [PULL 00/31] target-arm queue no-reply

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