* [RFC 0/5] target/riscv: Add support for BF16 extensions
@ 2023-04-12 2:33 Weiwei Li
2023-04-12 2:33 ` [RFC 1/5] target/riscv: Add properties " Weiwei Li
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Weiwei Li @ 2023-04-12 2:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Specification for BF16 extensions can be found in:
https://github.com/riscv/riscv-bfloat16
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream
Weiwei Li (5):
target/riscv: Add properties for BF16 extensions
target/riscv: Add support for Zfbfmin extension
target/riscv: Add support for Zvfbfmin extension
target/riscv: Add support for Zvfbfwma extension
target/riscv: Expose properties for BF16 extensions
target/riscv/cpu.c | 20 +++
target/riscv/cpu.h | 3 +
target/riscv/fpu_helper.c | 12 ++
target/riscv/helper.h | 10 ++
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 175 +++++++++++++++++++++
target/riscv/insn_trans/trans_rvzfh.c.inc | 13 +-
target/riscv/translate.c | 1 +
target/riscv/vector_helper.c | 17 ++
9 files changed, 257 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [RFC 1/5] target/riscv: Add properties for BF16 extensions
2023-04-12 2:33 [RFC 0/5] target/riscv: Add support for BF16 extensions Weiwei Li
@ 2023-04-12 2:33 ` Weiwei Li
2023-04-12 20:24 ` Daniel Henrique Barboza
2023-04-12 2:33 ` [RFC 2/5] target/riscv: Add support for Zfbfmin extension Weiwei Li
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Weiwei Li @ 2023-04-12 2:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 13 +++++++++++++
target/riscv/cpu.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..c19bbb41fb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -874,6 +874,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if ((cpu->cfg.ext_zfbfmin | cpu->cfg.ext_zvfbfmin |
+ cpu->cfg.ext_zvfbfwma) && !cpu->cfg.ext_f) {
+ error_setg(errp, "BF16 extensions require F extension");
+ return;
+ }
+
if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
error_setg(errp, "D extension requires F extension");
return;
@@ -918,6 +924,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if ((cpu->cfg.ext_zvfbfmin | cpu->cfg.ext_zvfbfwma) &&
+ !cpu->cfg.ext_zve32f) {
+ error_setg(errp, "Zvfbfmin/Zvfbfwma extensions require Zve32f "
+ "extension");
+ return;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zhinx) {
cpu->cfg.ext_zhinxmin = true;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..6c99a82624 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,6 +462,7 @@ struct RISCVCPUConfig {
bool ext_svpbmt;
bool ext_zdinx;
bool ext_zawrs;
+ bool ext_zfbfmin;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zfinx;
@@ -471,6 +472,8 @@ struct RISCVCPUConfig {
bool ext_zve64f;
bool ext_zve64d;
bool ext_zmmul;
+ bool ext_zvfbfmin;
+ bool ext_zvfbfwma;
bool ext_zvfh;
bool ext_zvfhmin;
bool ext_smaia;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC 2/5] target/riscv: Add support for Zfbfmin extension
2023-04-12 2:33 [RFC 0/5] target/riscv: Add support for BF16 extensions Weiwei Li
2023-04-12 2:33 ` [RFC 1/5] target/riscv: Add properties " Weiwei Li
@ 2023-04-12 2:33 ` Weiwei Li
2023-04-12 10:20 ` Richard Henderson
2023-04-12 2:33 ` [RFC 3/5] target/riscv: Add support for Zvfbfmin extension Weiwei Li
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Weiwei Li @ 2023-04-12 2:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Add trans_* and helper function for Zfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/fpu_helper.c | 12 +++++
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 53 ++++++++++++++++++++++
target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++---
target/riscv/translate.c | 1 +
6 files changed, 80 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 449d236df6..013b52f9e3 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -593,3 +593,15 @@ uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1)
float16 frs1 = check_nanbox_h(env, rs1);
return float16_to_float64(frs1, true, &env->fp_status);
}
+
+uint64_t helper_fcvt_bf16_s(CPURISCVState *env, uint64_t rs1)
+{
+ float32 frs1 = check_nanbox_s(env, rs1);
+ return nanbox_h(env, float32_to_bfloat16(frs1, &env->fp_status));
+}
+
+uint64_t helper_fcvt_s_bf16(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(env, rs1);
+ return nanbox_s(env, bfloat16_to_float32(frs1, &env->fp_status));
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 37b54e0991..7650168eb0 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1142,3 +1142,7 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+
+/* BF16 functions */
+DEF_HELPER_FLAGS_2(fcvt_bf16_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 73d5d1b045..874a5cb974 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -908,3 +908,7 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
# *** RV32 Zicond Standard Extension ***
czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r
czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
+
+# *** Zfbfmin Standard Extension ***
+fcvt_bf16_s 0100010 00100 ..... ... ..... 1010011 @r2_rm
+fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
new file mode 100644
index 0000000000..2a299075d8
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -0,0 +1,53 @@
+/*
+ * RISC-V translation routines for the BF16 Standard Extensions.
+ *
+* Copyright (c) 2020-2023 PLCT Lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZFBFMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zfbfmin) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFBFMIN(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_bf16_s(dest, cpu_env, src1);
+ gen_set_fpr_hs(ctx, a->rd, dest);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFBFMIN(ctx);
+
+ TCGv_i64 dest = dest_fpr(ctx, a->rd);
+ TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_bf16(dest, cpu_env, src1);
+ gen_set_fpr_hs(ctx, a->rd, dest);
+ mark_fs_dirty(ctx);
+ return true;
+}
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 74dde37ff7..8b1e2519bb 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,8 +28,8 @@
} \
} while (0)
-#define REQUIRE_ZFHMIN(ctx) do { \
- if (!ctx->cfg_ptr->ext_zfhmin) { \
+#define REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zfhmin && !ctx->cfg_ptr->ext_zfbfmin) { \
return false; \
} \
} while (0)
@@ -46,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -69,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -574,7 +574,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
@@ -594,7 +594,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
{
REQUIRE_FPU;
- REQUIRE_ZFHMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0ee8ee147d..836229e87f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1085,6 +1085,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
+#include "insn_trans/trans_rvbf16.c.inc"
#include "decode-xthead.c.inc"
#include "insn_trans/trans_xthead.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC 3/5] target/riscv: Add support for Zvfbfmin extension
2023-04-12 2:33 [RFC 0/5] target/riscv: Add support for BF16 extensions Weiwei Li
2023-04-12 2:33 ` [RFC 1/5] target/riscv: Add properties " Weiwei Li
2023-04-12 2:33 ` [RFC 2/5] target/riscv: Add support for Zfbfmin extension Weiwei Li
@ 2023-04-12 2:33 ` Weiwei Li
2023-04-12 10:21 ` Richard Henderson
2023-04-12 2:33 ` [RFC 4/5] target/riscv: Add support for Zvfbfwma extension Weiwei Li
2023-04-12 2:33 ` [RFC 5/5] target/riscv: Expose properties for BF16 extensions Weiwei Li
4 siblings, 1 reply; 11+ messages in thread
From: Weiwei Li @ 2023-04-12 2:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Add trans_* and helper function for Zvfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 64 ++++++++++++++++++++++
target/riscv/vector_helper.c | 6 ++
4 files changed, 77 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7650168eb0..5a0649112a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1146,3 +1146,6 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
/* BF16 functions */
DEF_HELPER_FLAGS_2(fcvt_bf16_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64)
+
+DEF_HELPER_5(vfncvtbf16_f_f_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 874a5cb974..57ce3a3c8b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -912,3 +912,7 @@ czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
# *** Zfbfmin Standard Extension ***
fcvt_bf16_s 0100010 00100 ..... ... ..... 1010011 @r2_rm
fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
+
+# *** Zvfbfmin Standard Extension ***
+vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
+vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 2a299075d8..8a7449e0c8 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -22,6 +22,12 @@
} \
} while (0)
+#define REQUIRE_ZVFBFMIN(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zvfbfmin) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
{
REQUIRE_FPU;
@@ -51,3 +57,61 @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt_s_bf16 *a)
mark_fs_dirty(ctx);
return true;
}
+
+static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFMIN(ctx);
+
+ if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+
+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
+ vreg_ofs(ctx, a->rs2), cpu_env,
+ ctx->cfg_ptr->vlen / 8,
+ ctx->cfg_ptr->vlen / 8, data,
+ gen_helper_vfncvtbf16_f_f_w);
+ mark_vs_dirty(ctx);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFMIN(ctx);
+
+ if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+
+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
+ vreg_ofs(ctx, a->rs2), cpu_env,
+ ctx->cfg_ptr->vlen / 8,
+ ctx->cfg_ptr->vlen / 8, data,
+ gen_helper_vfwcvtbf16_f_f_v);
+ mark_vs_dirty(ctx);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2423affe37..e4e7ac33d9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4514,6 +4514,9 @@ RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 4)
GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 8)
+RVVCALL(OPFVV1, vfwcvtbf16_f_f_v, WOP_UU_H, H4, H2, bfloat16_to_float32)
+GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4)
+
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
#define NOP_UU_B uint8_t, uint16_t, uint32_t
@@ -4558,6 +4561,9 @@ RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2)
GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4)
+RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16)
+GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2)
+
/*
*** Vector Reduction Operations
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC 4/5] target/riscv: Add support for Zvfbfwma extension
2023-04-12 2:33 [RFC 0/5] target/riscv: Add support for BF16 extensions Weiwei Li
` (2 preceding siblings ...)
2023-04-12 2:33 ` [RFC 3/5] target/riscv: Add support for Zvfbfmin extension Weiwei Li
@ 2023-04-12 2:33 ` Weiwei Li
2023-04-12 10:22 ` Richard Henderson
2023-04-12 2:33 ` [RFC 5/5] target/riscv: Expose properties for BF16 extensions Weiwei Li
4 siblings, 1 reply; 11+ messages in thread
From: Weiwei Li @ 2023-04-12 2:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Add trans_* and helper function for Zvfbfwma instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 58 ++++++++++++++++++++++
target/riscv/insn_trans/trans_rvzfh.c.inc | 13 ++---
target/riscv/vector_helper.c | 11 ++++
5 files changed, 83 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5a0649112a..afed7643c2 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1149,3 +1149,6 @@ DEF_HELPER_FLAGS_2(fcvt_s_bf16, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_5(vfncvtbf16_f_f_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 57ce3a3c8b..6817bf39b1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -916,3 +916,7 @@ fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
# *** Zvfbfmin Standard Extension ***
vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
+
+# *** Zvfbfwma Standard Extension ***
+vfwmaccbf16_vv 100011 . ..... ..... 001 ..... 1010111 @r_vm
+vfwmaccbf16_vf 100011 . ..... ..... 101 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 8a7449e0c8..ca646dca29 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -28,6 +28,12 @@
} \
} while (0)
+#define REQUIRE_ZVFBFWMA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zvfbfwma) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt_bf16_s *a)
{
REQUIRE_FPU;
@@ -115,3 +121,55 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
}
return false;
}
+
+static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFWMA(ctx);
+
+ if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
+ vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+
+ gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0),
+ vreg_ofs(ctx, a->rs1),
+ vreg_ofs(ctx, a->rs2), cpu_env,
+ ctx->cfg_ptr->vlen / 8,
+ ctx->cfg_ptr->vlen / 8, data,
+ gen_helper_vfwmaccbf16_vv);
+ mark_vs_dirty(ctx);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a) \
+{
+ REQUIRE_FPU;
+ REQUIRE_ZVFBFWMA(ctx);
+
+ if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) &&
+ vext_check_ds(ctx, a->rd, a->rs2, a->vm)) {
+ uint32_t data = 0;
+
+ gen_set_rm(ctx, RISCV_FRM_DYN);
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
+ data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
+ return opfvf_trans(a->rd, a->rs1, a->rs2, data,
+ gen_helper_vfwmaccbf16_vf, ctx);
+ }
+
+ return false;
+}
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 8b1e2519bb..9cf1f9f0e2 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,8 +28,9 @@
} \
} while (0)
-#define REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx) do { \
- if (!ctx->cfg_ptr->ext_zfhmin && !ctx->cfg_ptr->ext_zfbfmin) { \
+#define REQUIRE_ZFHMIN_OR_ZFBFMIN_OR_ZVFBFWMA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zfhmin && !ctx->cfg_ptr->ext_zfbfmin && \
+ !ctx->cfg_ptr->ext_zvfbfwma) { \
return false; \
} \
} while (0)
@@ -46,7 +47,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN_OR_ZVFBFWMA(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -69,7 +70,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN_OR_ZVFBFWMA(ctx);
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -574,7 +575,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN_OR_ZVFBFWMA(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
@@ -594,7 +595,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
{
REQUIRE_FPU;
- REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
+ REQUIRE_ZFHMIN_OR_ZFBFMIN_OR_ZVFBFWMA(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e4e7ac33d9..a8ab39ed8e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3541,6 +3541,17 @@ RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
GEN_VEXT_VF(vfwmacc_vf_h, 4)
GEN_VEXT_VF(vfwmacc_vf_w, 8)
+static uint32_t fwmaccbf16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
+{
+ return float32_muladd(bfloat16_to_float32(a, s),
+ bfloat16_to_float32(b, s), d, 0, s);
+}
+
+RVVCALL(OPFVV3, vfwmaccbf16_vv, WOP_UUU_H, H4, H2, H2, fwmaccbf16)
+GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4)
+RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmacc16)
+GEN_VEXT_VF(vfwmaccbf16_vf, 4)
+
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
return float32_muladd(float16_to_float32(a, true, s),
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [RFC 5/5] target/riscv: Expose properties for BF16 extensions
2023-04-12 2:33 [RFC 0/5] target/riscv: Add support for BF16 extensions Weiwei Li
` (3 preceding siblings ...)
2023-04-12 2:33 ` [RFC 4/5] target/riscv: Add support for Zvfbfwma extension Weiwei Li
@ 2023-04-12 2:33 ` Weiwei Li
2023-04-12 20:24 ` Daniel Henrique Barboza
4 siblings, 1 reply; 11+ messages in thread
From: Weiwei Li @ 2023-04-12 2:33 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c19bbb41fb..0265fae46f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -83,6 +83,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
+ ISA_EXT_DATA_ENTRY(zfbfmin, true, PRIV_VERSION_1_12_0, ext_zfbfmin),
ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
@@ -107,6 +108,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
+ ISA_EXT_DATA_ENTRY(zvfbfmin, true, PRIV_VERSION_1_12_0, ext_zvfbfmin),
+ ISA_EXT_DATA_ENTRY(zvfbfwma, true, PRIV_VERSION_1_12_0, ext_zvfbfwma),
ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
@@ -1469,6 +1472,10 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
+ DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
+ DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
+ DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
+
DEFINE_PROP_END_OF_LIST(),
};
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [RFC 2/5] target/riscv: Add support for Zfbfmin extension
2023-04-12 2:33 ` [RFC 2/5] target/riscv: Add support for Zfbfmin extension Weiwei Li
@ 2023-04-12 10:20 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2023-04-12 10:20 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser
On 4/12/23 04:33, Weiwei Li wrote:
> Add trans_* and helper function for Zfbfmin instructions.
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/fpu_helper.c | 12 +++++
> target/riscv/helper.h | 4 ++
> target/riscv/insn32.decode | 4 ++
> target/riscv/insn_trans/trans_rvbf16.c.inc | 53 ++++++++++++++++++++++
> target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++---
> target/riscv/translate.c | 1 +
> 6 files changed, 80 insertions(+), 6 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC 3/5] target/riscv: Add support for Zvfbfmin extension
2023-04-12 2:33 ` [RFC 3/5] target/riscv: Add support for Zvfbfmin extension Weiwei Li
@ 2023-04-12 10:21 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2023-04-12 10:21 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser
On 4/12/23 04:33, Weiwei Li wrote:
> Add trans_* and helper function for Zvfbfmin instructions.
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/helper.h | 3 +
> target/riscv/insn32.decode | 4 ++
> target/riscv/insn_trans/trans_rvbf16.c.inc | 64 ++++++++++++++++++++++
> target/riscv/vector_helper.c | 6 ++
> 4 files changed, 77 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC 4/5] target/riscv: Add support for Zvfbfwma extension
2023-04-12 2:33 ` [RFC 4/5] target/riscv: Add support for Zvfbfwma extension Weiwei Li
@ 2023-04-12 10:22 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2023-04-12 10:22 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser
On 4/12/23 04:33, Weiwei Li wrote:
> Add trans_* and helper function for Zvfbfwma instructions.
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/helper.h | 3 ++
> target/riscv/insn32.decode | 4 ++
> target/riscv/insn_trans/trans_rvbf16.c.inc | 58 ++++++++++++++++++++++
> target/riscv/insn_trans/trans_rvzfh.c.inc | 13 ++---
> target/riscv/vector_helper.c | 11 ++++
> 5 files changed, 83 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC 1/5] target/riscv: Add properties for BF16 extensions
2023-04-12 2:33 ` [RFC 1/5] target/riscv: Add properties " Weiwei Li
@ 2023-04-12 20:24 ` Daniel Henrique Barboza
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-04-12 20:24 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang, lazyparser
On 4/11/23 23:33, Weiwei Li wrote:
> Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
> Add require check for BF16 extensions.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 13 +++++++++++++
> target/riscv/cpu.h | 3 +++
> 2 files changed, 16 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e97473af2..c19bbb41fb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -874,6 +874,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if ((cpu->cfg.ext_zfbfmin | cpu->cfg.ext_zvfbfmin |
> + cpu->cfg.ext_zvfbfwma) && !cpu->cfg.ext_f) {
> + error_setg(errp, "BF16 extensions require F extension");
> + return;
> + }
> +
> if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
> error_setg(errp, "D extension requires F extension");
> return;
> @@ -918,6 +924,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if ((cpu->cfg.ext_zvfbfmin | cpu->cfg.ext_zvfbfwma) &&
> + !cpu->cfg.ext_zve32f) {
> + error_setg(errp, "Zvfbfmin/Zvfbfwma extensions require Zve32f "
> + "extension");
> + return;
> + }
> +
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_zhinx) {
> cpu->cfg.ext_zhinxmin = true;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 638e47c75a..6c99a82624 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -462,6 +462,7 @@ struct RISCVCPUConfig {
> bool ext_svpbmt;
> bool ext_zdinx;
> bool ext_zawrs;
> + bool ext_zfbfmin;
> bool ext_zfh;
> bool ext_zfhmin;
> bool ext_zfinx;
> @@ -471,6 +472,8 @@ struct RISCVCPUConfig {
> bool ext_zve64f;
> bool ext_zve64d;
> bool ext_zmmul;
> + bool ext_zvfbfmin;
> + bool ext_zvfbfwma;
> bool ext_zvfh;
> bool ext_zvfhmin;
> bool ext_smaia;
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [RFC 5/5] target/riscv: Expose properties for BF16 extensions
2023-04-12 2:33 ` [RFC 5/5] target/riscv: Expose properties for BF16 extensions Weiwei Li
@ 2023-04-12 20:24 ` Daniel Henrique Barboza
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-04-12 20:24 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang, lazyparser
On 4/11/23 23:33, Weiwei Li wrote:
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c19bbb41fb..0265fae46f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -83,6 +83,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
> ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
> ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
> + ISA_EXT_DATA_ENTRY(zfbfmin, true, PRIV_VERSION_1_12_0, ext_zfbfmin),
> ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
> ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
> ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
> @@ -107,6 +108,8 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
> ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
> ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
> + ISA_EXT_DATA_ENTRY(zvfbfmin, true, PRIV_VERSION_1_12_0, ext_zvfbfmin),
> + ISA_EXT_DATA_ENTRY(zvfbfwma, true, PRIV_VERSION_1_12_0, ext_zvfbfwma),
> ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
> ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
> ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
> @@ -1469,6 +1472,10 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
> DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
>
> + DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false),
> + DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false),
> + DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false),
> +
> DEFINE_PROP_END_OF_LIST(),
> };
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-04-12 20:24 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-12 2:33 [RFC 0/5] target/riscv: Add support for BF16 extensions Weiwei Li
2023-04-12 2:33 ` [RFC 1/5] target/riscv: Add properties " Weiwei Li
2023-04-12 20:24 ` Daniel Henrique Barboza
2023-04-12 2:33 ` [RFC 2/5] target/riscv: Add support for Zfbfmin extension Weiwei Li
2023-04-12 10:20 ` Richard Henderson
2023-04-12 2:33 ` [RFC 3/5] target/riscv: Add support for Zvfbfmin extension Weiwei Li
2023-04-12 10:21 ` Richard Henderson
2023-04-12 2:33 ` [RFC 4/5] target/riscv: Add support for Zvfbfwma extension Weiwei Li
2023-04-12 10:22 ` Richard Henderson
2023-04-12 2:33 ` [RFC 5/5] target/riscv: Expose properties for BF16 extensions Weiwei Li
2023-04-12 20:24 ` Daniel Henrique Barboza
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).