From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v9 04/11] target/riscv: add PRIV_VERSION_LATEST
Date: Wed, 17 May 2023 10:57:07 -0300 [thread overview]
Message-ID: <20230517135714.211809-5-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com>
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at once when a new priv version is
available.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 ++++----
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8ba86d54b2..b1a6675d1e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -345,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj)
VM_1_10_SV32 : VM_1_10_SV57);
#endif
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
}
#if defined(TARGET_RISCV64)
@@ -356,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, MXL_RV64, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -462,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj)
set_misa(env, MXL_RV128, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -475,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj)
set_misa(env, MXL_RV32, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de7e43126a..15423585d0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -61,6 +61,8 @@ enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
+
+ PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
};
#define VEXT_VERSION_1_00_0 0x00010000
--
2.40.1
next prev parent reply other threads:[~2023-05-17 13:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 13:57 [PATCH v9 00/11] target/riscv: rework CPU extension validation Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 01/11] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 02/11] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 03/11] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-05-17 13:57 ` Daniel Henrique Barboza [this message]
2023-05-17 13:57 ` [PATCH v9 05/11] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 06/11] target/riscv: Update check for Zca/Zcf/Zcd Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 07/11] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 08/11] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 09/11] target/riscv/cpu.c: validate extensions before riscv_timer_init() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 10/11] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 11/11] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-05-18 4:49 ` Alistair Francis
2023-05-18 9:45 ` [PATCH v9 00/11] target/riscv: rework CPU extension validation Alistair Francis
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