From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v9 05/11] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
Date: Wed, 17 May 2023 10:57:08 -0300 [thread overview]
Message-ID: <20230517135714.211809-6-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com>
From: Weiwei Li <liweiwei@iscas.ac.cn>
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them invisible to user
if the specified priv version is lower than their minimal priv version.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b1a6675d1e..88195945e5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1758,7 +1758,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int i;
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
+ if (cpu->env.priv_ver >= isa_edata_arr[i].min_version &&
+ isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
g_free(old);
old = new;
--
2.40.1
next prev parent reply other threads:[~2023-05-17 13:59 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 13:57 [PATCH v9 00/11] target/riscv: rework CPU extension validation Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 01/11] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 02/11] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 03/11] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 04/11] target/riscv: add PRIV_VERSION_LATEST Daniel Henrique Barboza
2023-05-17 13:57 ` Daniel Henrique Barboza [this message]
2023-05-17 13:57 ` [PATCH v9 06/11] target/riscv: Update check for Zca/Zcf/Zcd Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 07/11] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 08/11] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 09/11] target/riscv/cpu.c: validate extensions before riscv_timer_init() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 10/11] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Daniel Henrique Barboza
2023-05-17 13:57 ` [PATCH v9 11/11] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-05-18 4:49 ` Alistair Francis
2023-05-18 9:45 ` [PATCH v9 00/11] target/riscv: rework CPU extension validation Alistair Francis
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