From: Christoph Muellner <christoph.muellner@vrull.eu>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Richard Henderson <richard.henderson@linaro.org>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>,
"Alistair Francis" <Alistair.Francis@wdc.com>
Subject: [PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode
Date: Tue, 30 May 2023 15:18:39 +0200 [thread overview]
Message-ID: <20230530131843.1186637-6-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230530131843.1186637-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global variable opcode_data (which is renamed to rvi_opcode_data).
This patch does not introduce any functional change, but prepares
the code for more struct rv_opcode_data objects in the future.
This patch is based on previous work from Liu Zhiwei:
https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
disas/riscv.c | 9 ++++++++-
disas/riscv.h | 33 +++++++++++++++++----------------
2 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 4cf477bc02..086edee6a2 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1055,7 +1055,7 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
/* instruction metadata */
-const rv_opcode_data opcode_data[] = {
+const rv_opcode_data rvi_opcode_data[] = {
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
{ "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
@@ -3803,6 +3803,7 @@ static uint32_t operand_tbl_index(rv_inst inst)
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
rv_inst inst = dec->inst;
dec->codec = opcode_data[dec->op].codec;
switch (dec->codec) {
@@ -4284,6 +4285,7 @@ static void append(char *s1, const char *s2, size_t n)
static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
char tmp[64];
const char *fmt;
@@ -4517,6 +4519,7 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
static void decode_inst_lift_pseudo(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
if (!comp_data) {
return;
@@ -4535,6 +4538,7 @@ static void decode_inst_lift_pseudo(rv_decode *dec)
static void decode_inst_decompress_rv32(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
int decomp_op = opcode_data[dec->op].decomp_rv32;
if (decomp_op != rv_op_illegal) {
if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
@@ -4549,6 +4553,7 @@ static void decode_inst_decompress_rv32(rv_decode *dec)
static void decode_inst_decompress_rv64(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
int decomp_op = opcode_data[dec->op].decomp_rv64;
if (decomp_op != rv_op_illegal) {
if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
@@ -4563,6 +4568,7 @@ static void decode_inst_decompress_rv64(rv_decode *dec)
static void decode_inst_decompress_rv128(rv_decode *dec)
{
+ const rv_opcode_data *opcode_data = dec->opcode_data;
int decomp_op = opcode_data[dec->op].decomp_rv128;
if (decomp_op != rv_op_illegal) {
if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
@@ -4598,6 +4604,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
rv_decode dec = { 0 };
dec.pc = pc;
dec.inst = inst;
+ dec.opcode_data = rvi_opcode_data;
decode_inst_opcode(&dec, isa);
decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
diff --git a/disas/riscv.h b/disas/riscv.h
index de2623e3cc..188f03feeb 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -162,9 +162,26 @@ typedef enum {
/* structures */
+typedef struct {
+ const int op;
+ const rvc_constraint *constraints;
+} rv_comp_data;
+
+typedef struct {
+ const char * const name;
+ const rv_codec codec;
+ const char * const format;
+ const rv_comp_data *pseudo;
+ const short decomp_rv32;
+ const short decomp_rv64;
+ const short decomp_rv128;
+ const short decomp_data;
+} rv_opcode_data;
+
typedef struct {
uint64_t pc;
uint64_t inst;
+ const rv_opcode_data *opcode_data;
int32_t imm;
uint16_t op;
uint8_t codec;
@@ -184,11 +201,6 @@ typedef struct {
uint8_t rlist;
} rv_decode;
-typedef struct {
- const int op;
- const rvc_constraint *constraints;
-} rv_comp_data;
-
enum {
rv_op_illegal = 0
};
@@ -197,17 +209,6 @@ enum {
rvcd_imm_nz = 0x1
};
-typedef struct {
- const char * const name;
- const rv_codec codec;
- const char * const format;
- const rv_comp_data *pseudo;
- const short decomp_rv32;
- const short decomp_rv64;
- const short decomp_rv128;
- const short decomp_data;
-} rv_opcode_data;
-
/* instruction formats */
#define rv_fmt_none "O\t"
--
2.40.1
next prev parent reply other threads:[~2023-05-30 13:23 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 13:18 [PATCH 0/9] disas/riscv: Add vendor extension support Christoph Muellner
2023-05-30 13:18 ` [PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble Christoph Muellner
2023-05-30 13:18 ` [PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h Christoph Muellner
2023-06-12 3:21 ` Alistair Francis
2023-06-12 6:40 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 3/9] disas/riscv: Move types/constants to new header file Christoph Muellner
2023-06-09 2:04 ` LIU Zhiwei
2023-06-12 3:22 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value Christoph Muellner
2023-06-12 3:24 ` Alistair Francis
2023-06-12 6:48 ` LIU Zhiwei
2023-05-30 13:18 ` Christoph Muellner [this message]
2023-06-12 3:26 ` [PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode Alistair Francis
2023-05-30 13:18 ` [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler Christoph Muellner
2023-06-12 3:34 ` Alistair Francis
2023-06-12 6:25 ` LIU Zhiwei
2023-06-12 9:47 ` Christoph Müllner
2023-06-12 10:01 ` LIU Zhiwei
2023-06-12 10:04 ` Christoph Müllner
2023-06-12 11:56 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 7/9] disas/riscv: Provide infrastructure for vendor extensions Christoph Muellner
2023-06-08 13:04 ` LIU Zhiwei
2023-06-12 11:11 ` Christoph Müllner
2023-06-12 3:37 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 8/9] disas/riscv: Add support for XVentanaCondOps Christoph Muellner
2023-06-12 3:38 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 9/9] disas/riscv: Add support for XThead* instructions Christoph Muellner
2023-06-12 3:40 ` Alistair Francis
2023-06-06 17:38 ` [PATCH 0/9] disas/riscv: Add vendor extension support Daniel Henrique Barboza
2023-06-12 11:17 ` Christoph Müllner
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