From: Alistair Francis <alistair23@gmail.com>
To: Christoph Muellner <christoph.muellner@vrull.eu>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Richard Henderson <richard.henderson@linaro.org>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler
Date: Mon, 12 Jun 2023 13:34:43 +1000 [thread overview]
Message-ID: <CAKmqyKPkErk2ciZ-WqcYhNHCUv5x4UmcVbgJag_XODdPOLVm7A@mail.gmail.com> (raw)
In-Reply-To: <20230530131843.1186637-7-christoph.muellner@vrull.eu>
On Tue, May 30, 2023 at 11:20 PM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The disassembler needs the available extensions in order
> to properly decode instructions in case of overlapping
> encodings (e.g. for vendor extensions).
>
> Let's use the field 'disassemble_info::private_data' to store
> our RISCVCPUConfig pointer.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5b7818dbd1..6f0cd9a0bb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -819,6 +819,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> {
> RISCVCPU *cpu = RISCV_CPU(s);
> CPURISCVState *env = &cpu->env;
> + RISCVCPUConfig *cfg = &cpu->cfg;
> +
> + info->private_data = cfg;
>
> switch (env->xl) {
> case MXL_RV32:
> --
> 2.40.1
>
>
next prev parent reply other threads:[~2023-06-12 3:35 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 13:18 [PATCH 0/9] disas/riscv: Add vendor extension support Christoph Muellner
2023-05-30 13:18 ` [PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble Christoph Muellner
2023-05-30 13:18 ` [PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h Christoph Muellner
2023-06-12 3:21 ` Alistair Francis
2023-06-12 6:40 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 3/9] disas/riscv: Move types/constants to new header file Christoph Muellner
2023-06-09 2:04 ` LIU Zhiwei
2023-06-12 3:22 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value Christoph Muellner
2023-06-12 3:24 ` Alistair Francis
2023-06-12 6:48 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode Christoph Muellner
2023-06-12 3:26 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler Christoph Muellner
2023-06-12 3:34 ` Alistair Francis [this message]
2023-06-12 6:25 ` LIU Zhiwei
2023-06-12 9:47 ` Christoph Müllner
2023-06-12 10:01 ` LIU Zhiwei
2023-06-12 10:04 ` Christoph Müllner
2023-06-12 11:56 ` LIU Zhiwei
2023-05-30 13:18 ` [PATCH 7/9] disas/riscv: Provide infrastructure for vendor extensions Christoph Muellner
2023-06-08 13:04 ` LIU Zhiwei
2023-06-12 11:11 ` Christoph Müllner
2023-06-12 3:37 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 8/9] disas/riscv: Add support for XVentanaCondOps Christoph Muellner
2023-06-12 3:38 ` Alistair Francis
2023-05-30 13:18 ` [PATCH 9/9] disas/riscv: Add support for XThead* instructions Christoph Muellner
2023-06-12 3:40 ` Alistair Francis
2023-06-06 17:38 ` [PATCH 0/9] disas/riscv: Add vendor extension support Daniel Henrique Barboza
2023-06-12 11:17 ` Christoph Müllner
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