Re: [PATCH 0/9] disas/riscv: Add vendor extension support

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

Hi,

Can you please rebase on top of Alistair's riscv-to-apply.next and re-send?

Some patches can't be applied cleanly, in particular patch 2, which conflicts
with Weiwei's "target/riscv: Split RISCVCPUConfig declarations from cpu.h
into cpu_cfg.h" that landed into riscv-to-apply.next a few weeks ago. In
this particular case patch 2 of this series would need to move just the
bits of target/ppc/translate.c to the already existing cpu_cfg.h file.


Put me in the CC when you re-send and I'll review it asap. Thanks,


Daniel

On 5/30/23 10:18, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> This series adds vendor extension support to the QEMU disassembler
> for RISC-V. The following vendor extensions are covered:
> * XThead{Ba,Bb,Bs,Cmo,CondMov,FMemIdx,Fmv,Mac,MemIdx,MemPair,Sync}
> * XVentanaCondOps
> 
> So far, there have been two attempts to add vendor extension support
> to the QEMU disassembler. The first one [1] was posted in August 2022
> by LIU Zhiwei and attempts to separate vendor extension specifics
> from standard extension code in combination with a patch that introduced
> support for XVentanaCondOps. The second one [2] was posted in March 2023
> by me and added XThead* support without separating the vendor extensions
> from the standard code.
> 
> This patchset represents the third attempt to add vendor extension
> support to the QEMU disassembler. It adds all features of the previous
> attempts and integrates them into a patchset that uses the same
> mechanism for testing the extension availability like translate.c
> (using the booleans RISCVCPUConfig::ext_*).
> To achieve that, a couple of patches were needed to restructure
> the existing code.
> 
> Note, that this patchset allows an instruction encoder function for each
> vendor extension, but operand decoding and instruction printing remains
> common code. This is irrelevant for XVentanaCondOps, but the patch for
> the XThead* extensions includes changes in riscv.c and riscv.h.
> This could be changed to force more separation with the cost of
> duplication.
> 
> The first patch of this series is cherry-picked from LIU Zhiwei's series.
> It was reviewed by Alistair Francis and Richard Henderson, but never
> made it on master. I've added "Reviewed-by" tags to the commit.
> 
> I've added "Co-developed-by" tags to those commits that are derived
> from the series of LIU Zhiwei.
> 
> [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html
> [2] https://lists.nongnu.org/archive/html/qemu-devel/2023-03/msg04566.html
> 
> Christoph Müllner (8):
>    target/riscv: Factor out RISCVCPUConfig from cpu.h
>    disas/riscv: Move types/constants to new header file
>    disas/riscv: Make rv_op_illegal a shared enum value
>    disas/riscv: Encapsulate opcode_data into decode
>    target/riscv/cpu: Share RISCVCPUConfig with disassembler
>    disas/riscv: Provide infrastructure for vendor extensions
>    disas/riscv: Add support for XVentanaCondOps
>    disas/riscv: Add support for XThead* instructions
> 
> LIU Zhiwei (1):
>    target/riscv: Use xl instead of mxl for disassemble
> 
>   disas/meson.build         |   6 +-
>   disas/riscv-xthead.c      | 707 ++++++++++++++++++++++++++++++++++++++
>   disas/riscv-xthead.h      |  28 ++
>   disas/riscv-xventana.c    |  41 +++
>   disas/riscv-xventana.h    |  18 +
>   disas/riscv.c             | 384 ++++++---------------
>   disas/riscv.h             | 297 ++++++++++++++++
>   target/riscv/cpu-config.h | 159 +++++++++
>   target/riscv/cpu.c        |   6 +-
>   target/riscv/cpu.h        | 114 +-----
>   target/riscv/translate.c  |  27 +-
>   11 files changed, 1374 insertions(+), 413 deletions(-)
>   create mode 100644 disas/riscv-xthead.c
>   create mode 100644 disas/riscv-xthead.h
>   create mode 100644 disas/riscv-xventana.c
>   create mode 100644 disas/riscv-xventana.h
>   create mode 100644 disas/riscv.h
>   create mode 100644 target/riscv/cpu-config.h
>