* [PULL 00/60] riscv-to-apply queue
@ 2023-06-14 1:19 Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
` (61 more replies)
0 siblings, 62 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
Merge tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu into staging (2023-06-10 07:25:00 -0700)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. (2023-06-14 10:04:30 +1000)
----------------------------------------------------------------
Second RISC-V PR for 8.1
* Skip Vector set tail when vta is zero
* Move zc* out of the experimental properties
* Mask the implicitly enabled extensions in isa_string based on priv version
* Rework CPU extension validation and validate MISA changes
* Fixup PMP TLB cacheing errors
* Writing to pmpaddr and MML/MMWP correctly triggers TLB flushes
* Fixup PMP bypass checks
* Deny access if access is partially inside a PMP entry
* Correct OpenTitanState parent type/size
* Fix QEMU crash when NUMA nodes exceed available CPUs
* Fix pointer mask transformation for vector address
* Updates and improvements for Smstateen
* Support disas for Zcm* extensions
* Support disas for Z*inx extensions
* Remove unused decomp_rv32/64 value for vector instructions
* Enable PC-relative translation
* Assume M-mode FW in pflash0 only when "-bios none"
* Support using pflash via -blockdev option
* Add vector registers to log
* Clean up reference of Vector MTYPE
* Remove the check for extra Vector tail elements
* Smepmp: Return error when access permission not allowed in PMP
* Fixes for smsiaddrcfg and smsiaddrcfgh in AIA
----------------------------------------------------------------
Daniel Henrique Barboza (10):
target/riscv/vector_helper.c: skip set tail when vta is zero
target/riscv/cpu.c: add riscv_cpu_validate_v()
target/riscv/cpu.c: remove set_vext_version()
target/riscv/cpu.c: remove set_priv_version()
target/riscv: add PRIV_VERSION_LATEST
target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
target/riscv/cpu.c: validate extensions before riscv_timer_init()
target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
target/riscv: rework write_misa()
Himanshu Chauhan (1):
target/riscv: Smepmp: Return error when access permission not allowed in PMP
Ivan Klokov (1):
util/log: Add vector registers to log
Mayuresh Chitale (3):
target/riscv: smstateen check for fcsr
target/riscv: Reuse tb->flags.FS
target/riscv: smstateen knobs
Philippe Mathieu-Daudé (5):
hw/riscv/opentitan: Rename machine_[class]_init() functions
hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
hw/riscv/opentitan: Explicit machine type definition
hw/riscv/opentitan: Correct OpenTitanState parent type/size
Sunil V L (3):
hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
riscv/virt: Support using pflash via -blockdev option
docs/system: riscv: Add pflash usage details
Tommy Wu (1):
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
Weiwei Li (33):
target/riscv: Move zc* out of the experimental properties
target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
target/riscv: Update check for Zca/Zcf/Zcd
target/riscv: Update pmp_get_tlb_size()
target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
target/riscv: Make the short cut really work in pmp_hart_has_privs
target/riscv: Change the return type of pmp_hart_has_privs() to bool
target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
target/riscv: Flush TLB when MMWP or MML bits are changed
target/riscv: Update the next rule addr in pmpaddr_csr_write()
target/riscv: Flush TLB when pmpaddr is updated
target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
target/riscv: Deny access if access is partially inside the PMP entry
target/riscv: Fix pointer mask transformation for vector address
target/riscv: Update cur_pmmask/base when xl changes
disas: Change type of disassemble_info.target_info to pointer
target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
disas/riscv.c: Support disas for Zcm* extensions
disas/riscv.c: Support disas for Z*inx extensions
disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
disas/riscv.c: Fix lines with over 80 characters
disas/riscv.c: Remove redundant parentheses
target/riscv: Fix target address to update badaddr
target/riscv: Introduce cur_insn_len into DisasContext
target/riscv: Change gen_goto_tb to work on displacements
target/riscv: Change gen_set_pc_imm to gen_update_pc
target/riscv: Use true diff for gen_pc_plus_diff
target/riscv: Enable PC-relative translation
target/riscv: Remove pc_succ_insn from DisasContext
target/riscv: Fix initialized value for cur_pmmask
Xiao Wang (2):
target/riscv/vector_helper.c: clean up reference of MTYPE
target/riscv/vector_helper.c: Remove the check for extra tail elements
Yin Wang (1):
hw/riscv: qemu crash when NUMA nodes exceed available CPUs
docs/system/riscv/virt.rst | 31 +
include/disas/dis-asm.h | 2 +-
include/hw/core/cpu.h | 2 +
include/hw/riscv/opentitan.h | 6 +-
include/qemu/log.h | 1 +
target/riscv/cpu.h | 117 +--
target/riscv/cpu_cfg.h | 136 +++
target/riscv/pmp.h | 11 +-
accel/tcg/cpu-exec.c | 3 +
disas/riscv.c | 1194 +++++++++++++-----------
hw/intc/riscv_aplic.c | 4 +-
hw/riscv/numa.c | 6 +
hw/riscv/opentitan.c | 38 +-
hw/riscv/virt.c | 59 +-
target/riscv/cpu.c | 384 +++++---
target/riscv/cpu_helper.c | 37 +-
target/riscv/csr.c | 75 +-
target/riscv/pmp.c | 205 ++--
target/riscv/translate.c | 99 +-
target/riscv/vector_helper.c | 33 +-
util/log.c | 2 +
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
target/riscv/insn_trans/trans_rvf.c.inc | 21 +-
target/riscv/insn_trans/trans_rvi.c.inc | 46 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 +-
target/riscv/insn_trans/trans_rvzawrs.c.inc | 2 +-
target/riscv/insn_trans/trans_rvzce.c.inc | 10 +-
target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
29 files changed, 1442 insertions(+), 1102 deletions(-)
create mode 100644 target/riscv/cpu_cfg.h
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 02/60] target/riscv: Move zc* out of the experimental properties Alistair Francis
` (60 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Alistair Francis,
Palmer Dabbelt, Weiwei Li
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The function is a no-op if 'vta' is zero but we're still doing a lot of
stuff in this function regardless. vext_set_elems_1s() will ignore every
single time (since vta is zero) and we just wasted time.
Skip it altogether in this case. Aside from the code simplification
there's a noticeable emulation performance gain by doing it. For a
regular C binary that does a vectors operation like this:
=======
#define SZ 10000000
int main ()
{
int *a = malloc (SZ * sizeof (int));
int *b = malloc (SZ * sizeof (int));
int *c = malloc (SZ * sizeof (int));
for (int i = 0; i < SZ; i++)
c[i] = a[i] + b[i];
return c[SZ - 1];
}
=======
Emulating it with qemu-riscv64 and RVV takes ~0.3 sec:
$ time ~/work/qemu/build/qemu-riscv64 \
-cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out
real 0m0.303s
user 0m0.281s
sys 0m0.023s
With this skip we take ~0.275 sec:
$ time ~/work/qemu/build/qemu-riscv64 \
-cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out
real 0m0.274s
user 0m0.252s
sys 0m0.019s
This performance gain adds up fast when executing heavy benchmarks like
SPEC.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230427205708.246679-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f4d0438988..8e6c99e573 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -268,12 +268,17 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
void *vd, uint32_t desc, uint32_t nf,
uint32_t esz, uint32_t max_elems)
{
- uint32_t total_elems = vext_get_total_elems(env, desc, esz);
- uint32_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
+ uint32_t total_elems, vlenb, registers_used;
uint32_t vta = vext_vta(desc);
- uint32_t registers_used;
int k;
+ if (vta == 0) {
+ return;
+ }
+
+ total_elems = vext_get_total_elems(env, desc, esz);
+ vlenb = riscv_cpu_cfg(env)->vlen >> 3;
+
for (k = 0; k < nf; ++k) {
vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
(k * max_elems + max_elems) * esz);
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 02/60] target/riscv: Move zc* out of the experimental properties
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() Alistair Francis
` (59 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Zc* extensions (version 1.0) are ratified.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230510030040.20528-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db0875fb43..99ed9cb80e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1571,6 +1571,14 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
+ DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
+ DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
+ DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
+ DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
+ DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
+ DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
@@ -1588,14 +1596,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
- DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
- DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
- DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
- DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false),
- DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
- DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
- DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
-
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
2023-06-14 1:19 ` [PULL 02/60] target/riscv: Move zc* out of the experimental properties Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 04/60] target/riscv/cpu.c: remove set_vext_version() Alistair Francis
` (58 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(), after we've already set some
extensions that are dependent on RVV. Let's put it in its own function
and do it earlier.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 89 +++++++++++++++++++++++++---------------------
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 99ed9cb80e..1558a0b93f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -834,6 +834,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
}
}
+static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
+ Error **errp)
+{
+ int vext_version = VEXT_VERSION_1_00_0;
+
+ if (!is_power_of_2(cfg->vlen)) {
+ error_setg(errp, "Vector extension VLEN must be power of 2");
+ return;
+ }
+ if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
+ error_setg(errp,
+ "Vector extension implementation only supports VLEN "
+ "in the range [128, %d]", RV_VLEN_MAX);
+ return;
+ }
+ if (!is_power_of_2(cfg->elen)) {
+ error_setg(errp, "Vector extension ELEN must be power of 2");
+ return;
+ }
+ if (cfg->elen > 64 || cfg->elen < 8) {
+ error_setg(errp,
+ "Vector extension implementation only supports ELEN "
+ "in the range [8, 64]");
+ return;
+ }
+ if (cfg->vext_spec) {
+ if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
+ } else {
+ error_setg(errp, "Unsupported vector spec version '%s'",
+ cfg->vext_spec);
+ return;
+ }
+ } else {
+ qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
+ }
+ set_vext_version(env, vext_version);
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -841,6 +881,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
+ Error *local_err = NULL;
/* Do some ISA extension error checking */
if (riscv_has_ext(env, RVG) &&
@@ -909,8 +950,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- /* The V vector extension depends on the Zve64d extension */
if (riscv_has_ext(env, RVV)) {
+ riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ /* The V vector extension depends on the Zve64d extension */
cpu->cfg.ext_zve64d = true;
}
@@ -1045,46 +1092,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zksed = true;
cpu->cfg.ext_zksh = true;
}
-
- if (riscv_has_ext(env, RVV)) {
- int vext_version = VEXT_VERSION_1_00_0;
- if (!is_power_of_2(cpu->cfg.vlen)) {
- error_setg(errp,
- "Vector extension VLEN must be power of 2");
- return;
- }
- if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
- error_setg(errp,
- "Vector extension implementation only supports VLEN "
- "in the range [128, %d]", RV_VLEN_MAX);
- return;
- }
- if (!is_power_of_2(cpu->cfg.elen)) {
- error_setg(errp,
- "Vector extension ELEN must be power of 2");
- return;
- }
- if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
- error_setg(errp,
- "Vector extension implementation only supports ELEN "
- "in the range [8, 64]");
- return;
- }
- if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
- vext_version = VEXT_VERSION_1_00_0;
- } else {
- error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
- return;
- }
- } else {
- qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
- }
- set_vext_version(env, vext_version);
- }
}
#ifndef CONFIG_USER_ONLY
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 04/60] target/riscv/cpu.c: remove set_vext_version()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2023-06-14 1:19 ` [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Alistair Francis
` (57 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1558a0b93f..13d725dc20 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -252,11 +252,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
-static void set_vext_version(CPURISCVState *env, int vext_ver)
-{
- env->vext_ver = vext_ver;
-}
-
#ifndef CONFIG_USER_ONLY
static uint8_t satp_mode_from_str(const char *satp_mode_str)
{
@@ -871,7 +866,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
qemu_log("vector version is not specified, "
"use the default value v1.0\n");
}
- set_vext_version(env, vext_version);
+ env->vext_ver = vext_version;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 05/60] target/riscv/cpu.c: remove set_priv_version()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2023-06-14 1:19 ` [PULL 04/60] target/riscv/cpu.c: remove set_vext_version() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST Alistair Francis
` (56 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 13d725dc20..9fc9d1cc0f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -247,11 +247,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
env->misa_ext_mask = env->misa_ext = ext;
}
-static void set_priv_version(CPURISCVState *env, int priv_ver)
-{
- env->priv_ver = priv_ver;
-}
-
#ifndef CONFIG_USER_ONLY
static uint8_t satp_mode_from_str(const char *satp_mode_str)
{
@@ -350,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj)
VM_1_10_SV32 : VM_1_10_SV57);
#endif
- set_priv_version(env, PRIV_VERSION_1_12_0);
+ env->priv_ver = PRIV_VERSION_1_12_0;
}
#if defined(TARGET_RISCV64)
@@ -361,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, MXL_RV64, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- set_priv_version(env, PRIV_VERSION_1_12_0);
+ env->priv_ver = PRIV_VERSION_1_12_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -371,7 +366,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
+ env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
#endif
@@ -383,7 +378,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
+ env->priv_ver = PRIV_VERSION_1_10_0;
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -396,7 +391,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_11_0);
+ env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
@@ -467,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj)
set_misa(env, MXL_RV128, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- set_priv_version(env, PRIV_VERSION_1_12_0);
+ env->priv_ver = PRIV_VERSION_1_12_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -480,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj)
set_misa(env, MXL_RV32, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- set_priv_version(env, PRIV_VERSION_1_12_0);
+ env->priv_ver = PRIV_VERSION_1_12_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
@@ -490,7 +485,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
+ env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
@@ -502,7 +497,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
+ env->priv_ver = PRIV_VERSION_1_10_0;
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -515,7 +510,7 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_11_0);
+ env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -529,7 +524,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
+ env->priv_ver = PRIV_VERSION_1_10_0;
cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -1211,7 +1206,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (priv_version >= PRIV_VERSION_1_10_0) {
- set_priv_version(env, priv_version);
+ env->priv_ver = priv_version;
}
riscv_cpu_validate_misa_priv(env, &local_err);
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2023-06-14 1:19 ` [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Alistair Francis
` (55 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Richard Henderson,
LIU Zhiwei, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything at once when a new priv version is
available.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 8 ++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de7e43126a..15423585d0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -61,6 +61,8 @@ enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
+
+ PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
};
#define VEXT_VERSION_1_00_0 0x00010000
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9fc9d1cc0f..a0c4acfb47 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -345,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj)
VM_1_10_SV32 : VM_1_10_SV57);
#endif
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
}
#if defined(TARGET_RISCV64)
@@ -356,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, MXL_RV64, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -462,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj)
set_misa(env, MXL_RV128, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -475,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj)
set_misa(env, MXL_RV32, 0);
riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2023-06-14 1:19 ` [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd Alistair Francis
` (54 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv version to make them invisible to user
if the specified priv version is lower than their minimal priv version.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a0c4acfb47..81a785d525 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1758,7 +1758,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int i;
for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
+ if (cpu->env.priv_ver >= isa_edata_arr[i].min_version &&
+ isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
g_free(old);
old = new;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2023-06-14 1:19 ` [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Alistair Francis
` (53 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on the configured
priv version.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 5 +++--
target/riscv/insn_trans/trans_rvd.c.inc | 12 +++++++-----
target/riscv/insn_trans/trans_rvf.c.inc | 14 ++++++++------
target/riscv/insn_trans/trans_rvi.c.inc | 5 +++--
4 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 933b11c50d..29f1fb3995 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -551,7 +551,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
- if (!ctx->cfg_ptr->ext_zca) {
+ if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@@ -1125,7 +1125,8 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
* The Zca extension is added as way to refer to instructions in the C
* extension that do not include the floating-point loads and stores
*/
- if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) {
+ if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) &&
+ decode_insn16(ctx, opcode)) {
return;
}
} else {
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 2c51e01c40..6bdb55ef43 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -31,9 +31,11 @@
} \
} while (0)
-#define REQUIRE_ZCD(ctx) do { \
- if (!ctx->cfg_ptr->ext_zcd) { \
- return false; \
+#define REQUIRE_ZCD_OR_DC(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcd) { \
+ if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \
+ return false; \
+ } \
} \
} while (0)
@@ -67,13 +69,13 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
{
- REQUIRE_ZCD(ctx);
+ REQUIRE_ZCD_OR_DC(ctx);
return trans_fld(ctx, a);
}
static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
{
- REQUIRE_ZCD(ctx);
+ REQUIRE_ZCD_OR_DC(ctx);
return trans_fsd(ctx, a);
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index b2de4fcf3f..c47138575a 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -30,10 +30,12 @@
} \
} while (0)
-#define REQUIRE_ZCF(ctx) do { \
- if (!ctx->cfg_ptr->ext_zcf) { \
- return false; \
- } \
+#define REQUIRE_ZCF_OR_FC(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zcf) { \
+ if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \
+ return false; \
+ } \
+ } \
} while (0)
static bool trans_flw(DisasContext *ctx, arg_flw *a)
@@ -69,13 +71,13 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
{
- REQUIRE_ZCF(ctx);
+ REQUIRE_ZCF_OR_FC(ctx);
return trans_flw(ctx, a);
}
static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
{
- REQUIRE_ZCF(ctx);
+ REQUIRE_ZCF_OR_FC(ctx);
return trans_fsw(ctx, a);
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 2031e9931e..d794247f40 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
gen_set_pc(ctx, cpu_pc);
- if (!ctx->cfg_ptr->ext_zca) {
+ if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
@@ -169,7 +169,8 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
- if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
+ ((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (7 preceding siblings ...)
2023-06-14 1:19 ` [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Alistair Francis
` (52 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in riscv_cpu_validate_set_extensions() by accident. A
better place to put this code is at the end of
riscv_cpu_validate_set_extensions() after all the validations are
completed.
Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the
extesions after the validation is done. While we're at it, create a
riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related
validation to unclog riscv_cpu_realize a bit.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 91 ++++++++++++++++++++++++++++------------------
1 file changed, 56 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 81a785d525..a0589abb16 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -864,6 +864,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
env->vext_ver = vext_version;
}
+static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+{
+ CPURISCVState *env = &cpu->env;
+ int priv_version = -1;
+
+ if (cpu->cfg.priv_spec) {
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+ priv_version = PRIV_VERSION_1_12_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+ priv_version = PRIV_VERSION_1_11_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+ priv_version = PRIV_VERSION_1_10_0;
+ } else {
+ error_setg(errp,
+ "Unsupported privilege spec version '%s'",
+ cpu->cfg.priv_spec);
+ return;
+ }
+
+ env->priv_ver = priv_version;
+ }
+}
+
+static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+{
+ CPURISCVState *env = &cpu->env;
+ int i;
+
+ /* Force disable extensions if priv spec version does not match */
+ for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+ if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
+ (env->priv_ver < isa_edata_arr[i].min_version)) {
+ isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
+#ifndef CONFIG_USER_ONLY
+ warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+ " because privilege spec version does not match",
+ isa_edata_arr[i].name, env->mhartid);
+#else
+ warn_report("disabling %s extension because "
+ "privilege spec version does not match",
+ isa_edata_arr[i].name);
+#endif
+ }
+ }
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -1082,6 +1128,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zksed = true;
cpu->cfg.ext_zksh = true;
}
+
+ /*
+ * Disable isa extensions based on priv spec after we
+ * validated and set everything we need.
+ */
+ riscv_cpu_disable_priv_spec_isa_exts(cpu);
}
#ifndef CONFIG_USER_ONLY
@@ -1181,7 +1233,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
CPUClass *cc = CPU_CLASS(mcc);
- int i, priv_version = -1;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -1190,23 +1241,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- if (cpu->cfg.priv_spec) {
- if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
- priv_version = PRIV_VERSION_1_12_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
- priv_version = PRIV_VERSION_1_11_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
- priv_version = PRIV_VERSION_1_10_0;
- } else {
- error_setg(errp,
- "Unsupported privilege spec version '%s'",
- cpu->cfg.priv_spec);
- return;
- }
- }
-
- if (priv_version >= PRIV_VERSION_1_10_0) {
- env->priv_ver = priv_version;
+ riscv_cpu_validate_priv_spec(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
}
riscv_cpu_validate_misa_priv(env, &local_err);
@@ -1215,23 +1253,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- /* Force disable extensions if priv spec version does not match */
- for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
- (env->priv_ver < isa_edata_arr[i].min_version)) {
- isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
-#ifndef CONFIG_USER_ONLY
- warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
- " because privilege spec version does not match",
- isa_edata_arr[i].name, env->mhartid);
-#else
- warn_report("disabling %s extension because "
- "privilege spec version does not match",
- isa_edata_arr[i].name);
-#endif
- }
- }
-
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (8 preceding siblings ...)
2023-06-14 1:19 ` [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() Alistair Francis
` (51 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 50 ++++++++++++++++++++++++++++++----------------
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a0589abb16..89a1a25812 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -910,6 +910,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
}
}
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ CPUClass *cc = CPU_CLASS(mcc);
+ CPURISCVState *env = &cpu->env;
+
+ /* Validate that MISA_MXL is set properly. */
+ switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ case MXL_RV128:
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+ break;
+#endif
+ case MXL_RV32:
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (env->misa_mxl_max != env->misa_mxl) {
+ error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
+ return;
+ }
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -1232,7 +1259,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
- CPUClass *cc = CPU_CLASS(mcc);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -1241,6 +1267,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ riscv_cpu_validate_misa_mxl(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
riscv_cpu_validate_priv_spec(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -1269,22 +1301,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
#endif /* CONFIG_USER_ONLY */
- /* Validate that MISA_MXL is set properly. */
- switch (env->misa_mxl_max) {
-#ifdef TARGET_RISCV64
- case MXL_RV64:
- case MXL_RV128:
- cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
- break;
-#endif
- case MXL_RV32:
- cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
- default:
- g_assert_not_reached();
- }
- assert(env->misa_mxl_max == env->misa_mxl);
-
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (9 preceding siblings ...)
2023-06-14 1:19 ` [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Alistair Francis
` (50 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 89a1a25812..9f2c8fa7c6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1294,13 +1294,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
-
-#ifndef CONFIG_USER_ONLY
- if (cpu->cfg.ext_sstc) {
- riscv_timer_init(cpu);
- }
-#endif /* CONFIG_USER_ONLY */
-
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -1308,6 +1301,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.ext_sstc) {
+ riscv_timer_init(cpu);
+ }
+
if (cpu->cfg.pmu_num) {
if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (10 preceding siblings ...)
2023-06-14 1:19 ` [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 13/60] target/riscv: rework write_misa() Alistair Francis
` (49 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, LIU Zhiwei, Weiwei Li,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should always account for them. CPUs such as sifive_e need to
disable settings that aren't enabled simply because the parent class
happens to be enabling it.
Moving all configurations from the parent class to each CPU will
centralize the config of each CPU into its own init(), which is clearer
than having to account to whatever happens to be set in the parent
device. These settings are also being set in register_cpu_props() when
no 'misa_ext' is set, so for these CPUs we don't need changes. Named
CPUs will receive all cfgs that the parent were setting into their
init().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 59 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 47 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9f2c8fa7c6..778801dffc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -332,7 +332,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
static void riscv_any_cpu_init(Object *obj)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64)
@@ -346,6 +347,12 @@ static void riscv_any_cpu_init(Object *obj)
#endif
env->priv_ver = PRIV_VERSION_LATEST;
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
}
#if defined(TARGET_RISCV64)
@@ -364,12 +371,19 @@ static void rv64_base_cpu_init(Object *obj)
static void rv64_sifive_u_cpu_init(Object *obj)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
}
static void rv64_sifive_e_cpu_init(Object *obj)
@@ -379,10 +393,14 @@ static void rv64_sifive_e_cpu_init(Object *obj)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
static void rv64_thead_c906_cpu_init(Object *obj)
@@ -410,6 +428,9 @@ static void rv64_thead_c906_cpu_init(Object *obj)
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_SV39);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.pmp = true;
}
static void rv64_veyron_v1_cpu_init(Object *obj)
@@ -483,12 +504,19 @@ static void rv32_base_cpu_init(Object *obj)
static void rv32_sifive_u_cpu_init(Object *obj)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
}
static void rv32_sifive_e_cpu_init(Object *obj)
@@ -498,10 +526,14 @@ static void rv32_sifive_e_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
static void rv32_ibex_cpu_init(Object *obj)
@@ -511,11 +543,15 @@ static void rv32_ibex_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
cpu->cfg.epmp = true;
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
static void rv32_imafcu_nommu_cpu_init(Object *obj)
@@ -525,10 +561,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
- cpu->cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
#endif
+
+ /* inherited from parent obj via riscv_cpu_init() */
+ cpu->cfg.ext_ifencei = true;
+ cpu->cfg.ext_icsr = true;
+ cpu->cfg.pmp = true;
}
#endif
@@ -1441,11 +1481,6 @@ static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
- cpu->cfg.ext_ifencei = true;
- cpu->cfg.ext_icsr = true;
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 13/60] target/riscv: rework write_misa()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (11 preceding siblings ...)
2023-06-14 1:19 ` [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 14/60] target/riscv: Update pmp_get_tlb_size() Alistair Francis
` (48 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Weiwei Li, Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tweak first. When enabling RVG we're doing:
env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
env->misa_ext_mask = env->misa_ext;
This works fine for realize() time but this can potentially overwrite
env->misa_ext_mask if we reutilize the function for write_misa().
Instead of doing misa_ext_mask = misa_ext, sum up the RVG extensions in
misa_ext_mask as well. This won't change realize() time behavior
(misa_ext_mask will be == misa_ext) and will ensure that write_misa()
won't change misa_ext_mask by accident.
After that, rewrite write_misa() to work as follows:
- mask the write using misa_ext_mask to avoid enabling unsupported
extensions;
- suppress RVC if the next insn isn't aligned;
- disable RVG if any of RVG dependencies are being disabled by the user;
- assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On
error, rollback env->misa_ext to its original value, logging a
GUEST_ERROR to inform the user about the failed write;
- handle RVF and MSTATUS_FS and continue as usual.
Let's keep write_misa() as experimental for now until this logic gains
enough mileage.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230517135714.211809-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 4 ++--
target/riscv/csr.c | 51 ++++++++++++++++++++++------------------------
3 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 15423585d0..1f39edc687 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -548,6 +548,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 778801dffc..e67c78f860 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -981,7 +981,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
*/
-static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
@@ -997,7 +997,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_ifencei = true;
env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
- env->misa_ext_mask = env->misa_ext;
+ env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
}
if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4451bd1263..cf7da4f87f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1387,39 +1387,18 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
static RISCVException write_misa(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+ uint32_t orig_misa_ext = env->misa_ext;
+ Error *local_err = NULL;
+
if (!riscv_cpu_cfg(env)->misa_w) {
/* drop write to misa */
return RISCV_EXCP_NONE;
}
- /* 'I' or 'E' must be present */
- if (!(val & (RVI | RVE))) {
- /* It is not, drop write to misa */
- return RISCV_EXCP_NONE;
- }
-
- /* 'E' excludes all other extensions */
- if (val & RVE) {
- /*
- * when we support 'E' we can do "val = RVE;" however
- * for now we just drop writes if 'E' is present.
- */
- return RISCV_EXCP_NONE;
- }
-
- /*
- * misa.MXL writes are not supported by QEMU.
- * Drop writes to those bits.
- */
-
/* Mask extensions that are not supported by this hart */
val &= env->misa_ext_mask;
- /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
- if ((val & RVD) && !(val & RVF)) {
- val &= ~RVD;
- }
-
/*
* Suppress 'C' if next instruction is not aligned
* TODO: this should check next_pc
@@ -1428,18 +1407,36 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
val &= ~RVC;
}
+ /* Disable RVG if any of its dependencies are disabled */
+ if (!(val & RVI && val & RVM && val & RVA &&
+ val & RVF && val & RVD)) {
+ val &= ~RVG;
+ }
+
/* If nothing changed, do nothing. */
if (val == env->misa_ext) {
return RISCV_EXCP_NONE;
}
- if (!(val & RVF)) {
+ env->misa_ext = val;
+ riscv_cpu_validate_set_extensions(cpu, &local_err);
+ if (local_err != NULL) {
+ /* Rollback on validation error */
+ qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value "
+ "0x%x, keeping existing MISA ext 0x%x\n",
+ env->misa_ext, orig_misa_ext);
+
+ env->misa_ext = orig_misa_ext;
+
+ return RISCV_EXCP_NONE;
+ }
+
+ if (!(env->misa_ext & RVF)) {
env->mstatus &= ~MSTATUS_FS;
}
/* flush translation cache */
tb_flush(env_cpu(env));
- env->misa_ext = val;
env->xl = riscv_cpu_mxl(env);
return RISCV_EXCP_NONE;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 14/60] target/riscv: Update pmp_get_tlb_size()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (12 preceding siblings ...)
2023-06-14 1:19 ` [PULL 13/60] target/riscv: rework write_misa() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Alistair Francis
` (47 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~
0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot
cache the translation result in the TLB since this will make the write access
to 0x80000008 bypass the check of PMP0. So we should check all of them instead
of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in
this case.
Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.h | 3 +-
target/riscv/cpu_helper.c | 7 ++--
target/riscv/pmp.c | 69 ++++++++++++++++++++++++++++++---------
3 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index b296ea1fc6..0a7e24750b 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -76,8 +76,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
target_ulong size, pmp_priv_t privs,
pmp_priv_t *allowed_privs,
target_ulong mode);
-target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
- target_ulong tlb_sa, target_ulong tlb_ea);
+target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
uint32_t pmp_get_num_rules(CPURISCVState *env);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 56381aaf26..065b433b88 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -715,11 +715,8 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
}
*prot = pmp_priv_to_page_prot(pmp_priv);
- if ((tlb_size != NULL) && pmp_index != MAX_RISCV_PMPS) {
- target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
- target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
-
- *tlb_size = pmp_get_tlb_size(env, pmp_index, tlb_sa, tlb_ea);
+ if (tlb_size != NULL) {
+ *tlb_size = pmp_get_tlb_size(env, addr);
}
return TRANSLATE_SUCCESS;
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 1f5aca42e8..2bc924340a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -601,28 +601,67 @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
}
/*
- * Calculate the TLB size if the start address or the end address of
- * PMP entry is presented in the TLB page.
+ * Calculate the TLB size.
+ * It's possible that PMP regions only cover partial of the TLB page, and
+ * this may split the page into regions with different permissions.
+ * For example if PMP0 is (0x80000008~0x8000000F, R) and PMP1 is (0x80000000
+ * ~0x80000FFF, RWX), then region 0x80000008~0x8000000F has R permission, and
+ * the other regions in this page have RWX permissions.
+ * A write access to 0x80000000 will match PMP1. However we cannot cache the
+ * translation result in the TLB since this will make the write access to
+ * 0x80000008 bypass the check of PMP0.
+ * To avoid this we return a size of 1 (which means no caching) if the PMP
+ * region only covers partial of the TLB page.
*/
-target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index,
- target_ulong tlb_sa, target_ulong tlb_ea)
+target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr)
{
- target_ulong pmp_sa = env->pmp_state.addr[pmp_index].sa;
- target_ulong pmp_ea = env->pmp_state.addr[pmp_index].ea;
+ target_ulong pmp_sa;
+ target_ulong pmp_ea;
+ target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
+ target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
+ int i;
- if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) {
+ /*
+ * If PMP is not supported or there are no PMP rules, the TLB page will not
+ * be split into regions with different permissions by PMP so we set the
+ * size to TARGET_PAGE_SIZE.
+ */
+ if (!riscv_cpu_cfg(env)->pmp || !pmp_get_num_rules(env)) {
return TARGET_PAGE_SIZE;
- } else {
+ }
+
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) == PMP_AMATCH_OFF) {
+ continue;
+ }
+
+ pmp_sa = env->pmp_state.addr[i].sa;
+ pmp_ea = env->pmp_state.addr[i].ea;
+
/*
- * At this point we have a tlb_size that is the smallest possible size
- * That fits within a TARGET_PAGE_SIZE and the PMP region.
- *
- * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
- * This means the result isn't cached in the TLB and is only used for
- * a single translation.
+ * Only the first PMP entry that covers (whole or partial of) the TLB
+ * page really matters:
+ * If it covers the whole TLB page, set the size to TARGET_PAGE_SIZE,
+ * since the following PMP entries have lower priority and will not
+ * affect the permissions of the page.
+ * If it only covers partial of the TLB page, set the size to 1 since
+ * the allowed permissions of the region may be different from other
+ * region of the page.
*/
- return 1;
+ if (pmp_sa <= tlb_sa && pmp_ea >= tlb_ea) {
+ return TARGET_PAGE_SIZE;
+ } else if ((pmp_sa >= tlb_sa && pmp_sa <= tlb_ea) ||
+ (pmp_ea >= tlb_sa && pmp_ea <= tlb_ea)) {
+ return 1;
+ }
}
+
+ /*
+ * If no PMP entry matches the TLB page, the TLB page will also not be
+ * split into regions with different permissions by PMP so we set the size
+ * to TARGET_PAGE_SIZE.
+ */
+ return TARGET_PAGE_SIZE;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (13 preceding siblings ...)
2023-06-14 1:19 ` [PULL 14/60] target/riscv: Update pmp_get_tlb_size() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs Alistair Francis
` (46 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
pmp_get_tlb_size can be separated from get_physical_address_pmp and is only
needed when ret == TRANSLATE_SUCCESS.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 065b433b88..52d0b043df 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -688,14 +688,11 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
*
* @env: CPURISCVState
* @prot: The returned protection attributes
- * @tlb_size: TLB page size containing addr. It could be modified after PMP
- * permission checking. NULL if not set TLB page for addr.
* @addr: The physical address to be checked permission
* @access_type: The type of MMU access
* @mode: Indicates current privilege level.
*/
-static int get_physical_address_pmp(CPURISCVState *env, int *prot,
- target_ulong *tlb_size, hwaddr addr,
+static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
int size, MMUAccessType access_type,
int mode)
{
@@ -715,9 +712,6 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
}
*prot = pmp_priv_to_page_prot(pmp_priv);
- if (tlb_size != NULL) {
- *tlb_size = pmp_get_tlb_size(env, addr);
- }
return TRANSLATE_SUCCESS;
}
@@ -906,7 +900,7 @@ restart:
}
int pmp_prot;
- int pmp_ret = get_physical_address_pmp(env, &pmp_prot, NULL, pte_addr,
+ int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
sizeof(target_ulong),
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
@@ -1302,8 +1296,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
prot &= prot2;
if (ret == TRANSLATE_SUCCESS) {
- ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ ret = get_physical_address_pmp(env, &prot_pmp, pa,
size, access_type, mode);
+ tlb_size = pmp_get_tlb_size(env, pa);
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
@@ -1335,8 +1330,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
- ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
+ ret = get_physical_address_pmp(env, &prot_pmp, pa,
size, access_type, mode);
+ tlb_size = pmp_get_tlb_size(env, pa);
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (14 preceding siblings ...)
2023-06-14 1:19 ` [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool Alistair Francis
` (45 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Return the result directly for short cut, since We needn't do the
following check on the PMP entries if there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2bc924340a..3c90562d55 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -316,6 +316,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
allowed_privs, mode)) {
ret = MAX_RISCV_PMPS;
}
+ return ret;
}
if (size == 0) {
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (15 preceding siblings ...)
2023-06-14 1:19 ` [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Alistair Francis
` (44 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
We no longer need the pmp_index for matched PMP entry now.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.h | 8 ++++----
target/riscv/cpu_helper.c | 8 ++++----
target/riscv/pmp.c | 32 +++++++++++++-------------------
3 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 0a7e24750b..cf5c99f8e6 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -72,10 +72,10 @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
-int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs,
- pmp_priv_t *allowed_privs,
- target_ulong mode);
+bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+ target_ulong size, pmp_priv_t privs,
+ pmp_priv_t *allowed_privs,
+ target_ulong mode);
target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 52d0b043df..35ddd0caac 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -697,16 +697,16 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
int mode)
{
pmp_priv_t pmp_priv;
- int pmp_index = -1;
+ bool pmp_has_privs;
if (!riscv_cpu_cfg(env)->pmp) {
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TRANSLATE_SUCCESS;
}
- pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
- &pmp_priv, mode);
- if (pmp_index < 0) {
+ pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type,
+ &pmp_priv, mode);
+ if (!pmp_has_privs) {
*prot = 0;
return TRANSLATE_PMP_FAIL;
}
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3c90562d55..0684047b86 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -296,27 +296,23 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
/*
* Check if the address has required RWX privs to complete desired operation
- * Return PMP rule index if a pmp rule match
- * Return MAX_RISCV_PMPS if default match
- * Return negtive value if no match
+ * Return true if a pmp rule match or default match
+ * Return false if no match
*/
-int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs,
- pmp_priv_t *allowed_privs, target_ulong mode)
+bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+ target_ulong size, pmp_priv_t privs,
+ pmp_priv_t *allowed_privs, target_ulong mode)
{
int i = 0;
- int ret = -1;
+ bool ret = false;
int pmp_size = 0;
target_ulong s = 0;
target_ulong e = 0;
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
- if (pmp_hart_has_privs_default(env, addr, size, privs,
- allowed_privs, mode)) {
- ret = MAX_RISCV_PMPS;
- }
- return ret;
+ return pmp_hart_has_privs_default(env, addr, size, privs,
+ allowed_privs, mode);
}
if (size == 0) {
@@ -345,7 +341,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
if ((s + e) == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"pmp violation - access is partially inside\n");
- ret = -1;
+ ret = false;
break;
}
@@ -453,17 +449,15 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
* defined with PMP must be used. We shouldn't fallback on
* finding default privileges.
*/
- ret = i;
+ ret = true;
break;
}
}
/* No rule matched */
- if (ret == -1) {
- if (pmp_hart_has_privs_default(env, addr, size, privs,
- allowed_privs, mode)) {
- ret = MAX_RISCV_PMPS;
- }
+ if (!ret) {
+ ret = pmp_hart_has_privs_default(env, addr, size, privs,
+ allowed_privs, mode);
}
return ret;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (16 preceding siblings ...)
2023-06-14 1:19 ` [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Alistair Francis
` (43 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
RLB/MML/MMWP bits in mseccfg CSR are introduced by Smepmp extension.
So they can only be writable and set to 1s when cfg.epmp is true.
Then we also need't check on epmp in pmp_hart_has_privs_default().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 50 ++++++++++++++++++++++++----------------------
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 0684047b86..9a6e04cda0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -243,30 +243,28 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
{
bool ret;
- if (riscv_cpu_cfg(env)->epmp) {
- if (MSECCFG_MMWP_ISSET(env)) {
- /*
- * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
- * so we default to deny all, even for M-mode.
- */
+ if (MSECCFG_MMWP_ISSET(env)) {
+ /*
+ * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
+ * so we default to deny all, even for M-mode.
+ */
+ *allowed_privs = 0;
+ return false;
+ } else if (MSECCFG_MML_ISSET(env)) {
+ /*
+ * The Machine Mode Lockdown (mseccfg.MML) bit is set
+ * so we can only execute code in M-mode with an applicable
+ * rule. Other modes are disabled.
+ */
+ if (mode == PRV_M && !(privs & PMP_EXEC)) {
+ ret = true;
+ *allowed_privs = PMP_READ | PMP_WRITE;
+ } else {
+ ret = false;
*allowed_privs = 0;
- return false;
- } else if (MSECCFG_MML_ISSET(env)) {
- /*
- * The Machine Mode Lockdown (mseccfg.MML) bit is set
- * so we can only execute code in M-mode with an applicable
- * rule. Other modes are disabled.
- */
- if (mode == PRV_M && !(privs & PMP_EXEC)) {
- ret = true;
- *allowed_privs = PMP_READ | PMP_WRITE;
- } else {
- ret = false;
- *allowed_privs = 0;
- }
-
- return ret;
}
+
+ return ret;
}
if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
@@ -580,8 +578,12 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
}
}
- /* Sticky bits */
- val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ if (riscv_cpu_cfg(env)->epmp) {
+ /* Sticky bits */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ } else {
+ val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
+ }
env->mseccfg = val;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (17 preceding siblings ...)
2023-06-14 1:19 ` [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed Alistair Francis
` (42 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
The addr and size parameters in pmp_hart_has_privs_default() are unused.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9a6e04cda0..2403039133 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -236,8 +236,7 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
/*
* Check if the address has required RWX privs when no PMP entry is matched.
*/
-static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
- target_ulong size, pmp_priv_t privs,
+static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t privs,
pmp_priv_t *allowed_privs,
target_ulong mode)
{
@@ -309,8 +308,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
- return pmp_hart_has_privs_default(env, addr, size, privs,
- allowed_privs, mode);
+ return pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
}
if (size == 0) {
@@ -454,8 +452,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* No rule matched */
if (!ret) {
- ret = pmp_hart_has_privs_default(env, addr, size, privs,
- allowed_privs, mode);
+ ret = pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
}
return ret;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (18 preceding siblings ...)
2023-06-14 1:19 ` [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() Alistair Francis
` (41 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2403039133..4d62dfc732 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -578,6 +578,9 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
if (riscv_cpu_cfg(env)->epmp) {
/* Sticky bits */
val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+ if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+ tlb_flush(env_cpu(env));
+ }
} else {
val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write()
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (19 preceding siblings ...)
2023-06-14 1:19 ` [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated Alistair Francis
` (40 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Currently only the rule addr of the same index of pmpaddr is updated
when pmpaddr CSR is modified. However, the rule addr of next PMP entry
may also be affected if its A field is PMP_AMATCH_TOR. So we should
also update it in this case.
Write to pmpaddr CSR will not affect the rule nums, So we needn't update
call pmp_update_rule_nums() in pmpaddr_csr_write().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 4d62dfc732..48a3e44a77 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -507,6 +507,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val)
{
trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
+ bool is_next_cfg_tor = false;
if (addr_index < MAX_RISCV_PMPS) {
/*
@@ -515,9 +516,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
*/
if (addr_index + 1 < MAX_RISCV_PMPS) {
uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
+ is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg);
- if (pmp_cfg & PMP_LOCK &&
- PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
+ if (pmp_cfg & PMP_LOCK && is_next_cfg_tor) {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - pmpcfg + 1 locked\n");
return;
@@ -526,7 +527,10 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
if (!pmp_is_locked(env, addr_index)) {
env->pmp_state.pmp[addr_index].addr_reg = val;
- pmp_update_rule(env, addr_index);
+ pmp_update_rule_addr(env, addr_index);
+ if (is_next_cfg_tor) {
+ pmp_update_rule_addr(env, addr_index + 1);
+ }
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (20 preceding siblings ...)
2023-06-14 1:19 ` [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Alistair Francis
` (39 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis, LIU Zhiwei
From: Weiwei Li <liweiwei@iscas.ac.cn>
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230517091519.34439-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 48a3e44a77..e0acee7a15 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -531,6 +531,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
if (is_next_cfg_tor) {
pmp_update_rule_addr(env, addr_index + 1);
}
+ tlb_flush(env_cpu(env));
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (21 preceding siblings ...)
2023-06-14 1:19 ` [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Alistair Francis
` (38 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis, LIU Zhiwei
From: Weiwei Li <liweiwei@iscas.ac.cn>
TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230517091519.34439-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index e0acee7a15..3c12690565 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -26,7 +26,7 @@
#include "trace.h"
#include "exec/exec-all.h"
-static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
+static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
@@ -83,7 +83,7 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
* Accessor to set the cfg reg for a specific PMP/HART
* Bounds checks and relevant lock bit.
*/
-static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
+static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
@@ -119,14 +119,17 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
if (locked) {
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
- } else {
+ } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
+ return true;
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - out of bounds\n");
}
+
+ return false;
}
static void pmp_decode_napot(target_ulong a, target_ulong *sa,
@@ -467,16 +470,19 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
int i;
uint8_t cfg_val;
int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
+ bool modified = false;
trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
for (i = 0; i < pmpcfg_nums; i++) {
cfg_val = (val >> 8 * i) & 0xff;
- pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
+ modified |= pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
}
/* If PMP permission of any addr has been changed, flush TLB pages. */
- tlb_flush(env_cpu(env));
+ if (modified) {
+ tlb_flush(env_cpu(env));
+ }
}
@@ -526,12 +532,14 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
}
if (!pmp_is_locked(env, addr_index)) {
- env->pmp_state.pmp[addr_index].addr_reg = val;
- pmp_update_rule_addr(env, addr_index);
- if (is_next_cfg_tor) {
- pmp_update_rule_addr(env, addr_index + 1);
+ if (env->pmp_state.pmp[addr_index].addr_reg != val) {
+ env->pmp_state.pmp[addr_index].addr_reg = val;
+ pmp_update_rule_addr(env, addr_index);
+ if (is_next_cfg_tor) {
+ pmp_update_rule_addr(env, addr_index + 1);
+ }
+ tlb_flush(env_cpu(env));
}
- tlb_flush(env_cpu(env));
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (22 preceding siblings ...)
2023-06-14 1:19 ` [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry Alistair Francis
` (37 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use pmp_update_rule_addr() and pmp_update_rule_nums() separately to
update rule nums only once for each pmpcfg_csr_write. Then remove
pmp_update_rule() since it become unused.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-12-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 3c12690565..37e9985d6a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -29,7 +29,6 @@
static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
/*
* Accessor method to extract address matching type 'a field' from cfg reg
@@ -121,7 +120,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
} else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
- pmp_update_rule(env, pmp_index);
+ pmp_update_rule_addr(env, pmp_index);
return true;
}
} else {
@@ -209,18 +208,6 @@ void pmp_update_rule_nums(CPURISCVState *env)
}
}
-/*
- * Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
- * end address values.
- * This function is called relatively infrequently whereas the check that
- * an address is within a pmp rule is called often, so optimise that one
- */
-static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
-{
- pmp_update_rule_addr(env, pmp_index);
- pmp_update_rule_nums(env);
-}
-
static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
target_ulong addr)
{
@@ -481,6 +468,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
/* If PMP permission of any addr has been changed, flush TLB pages. */
if (modified) {
+ pmp_update_rule_nums(env);
tlb_flush(env_cpu(env));
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (23 preceding siblings ...)
2023-06-14 1:19 ` [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Alistair Francis
` (36 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Access will fail if access is partially inside the PMP entry.
However,only setting ret = false doesn't really mean pmp violation
since pmp_hart_has_privs_default() may return true at the end of
pmp_hart_has_privs().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-13-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 37e9985d6a..418738afd8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -327,8 +327,8 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
if ((s + e) == 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"pmp violation - access is partially inside\n");
- ret = false;
- break;
+ *allowed_privs = 0;
+ return false;
}
/* fully inside */
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (24 preceding siblings ...)
2023-06-14 1:19 ` [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Alistair Francis
` (35 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philippe Mathieu-Daudé,
Alistair Francis, Daniel Henrique Barboza
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Follow QOM style which declares FOO_init() as instance
initializer and FOO_class_init() as class initializer:
rename the OpenTitan machine class/instance init()
accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index bc678766e7..2d21ee39c5 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -75,7 +75,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
-static void opentitan_board_init(MachineState *machine)
+static void opentitan_machine_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const MemMapEntry *memmap = ibex_memmap;
@@ -108,17 +108,17 @@ static void opentitan_board_init(MachineState *machine)
}
}
-static void opentitan_machine_init(MachineClass *mc)
+static void opentitan_machine_class_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with OpenTitan";
- mc->init = opentitan_board_init;
+ mc->init = opentitan_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
mc->default_ram_id = "riscv.lowrisc.ibex.ram";
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE("opentitan", opentitan_machine_init)
+DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
static void lowrisc_ibex_soc_init(Object *obj)
{
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (25 preceding siblings ...)
2023-06-14 1:19 ` [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Alistair Francis
` (34 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philippe Mathieu-Daudé,
Alistair Francis, Daniel Henrique Barboza
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination. This
is in preparation of adding the OpenTitan machine type to
this array in a pair of commits.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 2d21ee39c5..294955eeea 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -320,17 +320,14 @@ static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
-static const TypeInfo lowrisc_ibex_soc_type_info = {
- .name = TYPE_RISCV_IBEX_SOC,
- .parent = TYPE_DEVICE,
- .instance_size = sizeof(LowRISCIbexSoCState),
- .instance_init = lowrisc_ibex_soc_init,
- .class_init = lowrisc_ibex_soc_class_init,
+static const TypeInfo open_titan_types[] = {
+ {
+ .name = TYPE_RISCV_IBEX_SOC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(LowRISCIbexSoCState),
+ .instance_init = lowrisc_ibex_soc_init,
+ .class_init = lowrisc_ibex_soc_class_init,
+ }
};
-static void lowrisc_ibex_soc_register_types(void)
-{
- type_register_static(&lowrisc_ibex_soc_type_info);
-}
-
-type_init(lowrisc_ibex_soc_register_types)
+DEFINE_TYPES(open_titan_types)
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (26 preceding siblings ...)
2023-06-14 1:19 ` [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition Alistair Francis
` (33 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philippe Mathieu-Daudé,
Alistair Francis, Daniel Henrique Barboza
From: Philippe Mathieu-Daudé <philmd@linaro.org>
QOM type names are usually defined as TYPE_FOO.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-4-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index c40b05052a..fd70226ed8 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -53,6 +53,8 @@ struct LowRISCIbexSoCState {
MemoryRegion flash_alias;
};
+#define TYPE_OPENTITAN_MACHINE "opentitan"
+
typedef struct OpenTitanState {
/*< private >*/
SysBusDevice parent_obj;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 294955eeea..7d7159ea30 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -118,7 +118,7 @@ static void opentitan_machine_class_init(MachineClass *mc)
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE("opentitan", opentitan_machine_class_init)
+DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
static void lowrisc_ibex_soc_init(Object *obj)
{
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (27 preceding siblings ...)
2023-06-14 1:19 ` [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Alistair Francis
` (32 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philippe Mathieu-Daudé,
Alistair Francis, Daniel Henrique Barboza
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Expand the DEFINE_MACHINE() macro, converting the class_init()
handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-5-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 3 ++-
hw/riscv/opentitan.c | 10 +++++++---
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index fd70226ed8..806ff73528 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -24,6 +24,7 @@
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "hw/ssi/ibex_spi_host.h"
+#include "hw/boards.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@@ -53,7 +54,7 @@ struct LowRISCIbexSoCState {
MemoryRegion flash_alias;
};
-#define TYPE_OPENTITAN_MACHINE "opentitan"
+#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
typedef struct OpenTitanState {
/*< private >*/
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 7d7159ea30..9535308197 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -108,8 +108,10 @@ static void opentitan_machine_init(MachineState *machine)
}
}
-static void opentitan_machine_class_init(MachineClass *mc)
+static void opentitan_machine_class_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "RISC-V Board compatible with OpenTitan";
mc->init = opentitan_machine_init;
mc->max_cpus = 1;
@@ -118,8 +120,6 @@ static void opentitan_machine_class_init(MachineClass *mc)
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
}
-DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init)
-
static void lowrisc_ibex_soc_init(Object *obj)
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
@@ -327,6 +327,10 @@ static const TypeInfo open_titan_types[] = {
.instance_size = sizeof(LowRISCIbexSoCState),
.instance_init = lowrisc_ibex_soc_init,
.class_init = lowrisc_ibex_soc_class_init,
+ }, {
+ .name = TYPE_OPENTITAN_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = opentitan_machine_class_init,
}
};
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (28 preceding siblings ...)
2023-06-14 1:19 ` [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs Alistair Francis
` (31 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Philippe Mathieu-Daudé,
Alistair Francis, Daniel Henrique Barboza
From: Philippe Mathieu-Daudé <philmd@linaro.org>
OpenTitanState is the 'machine' (or 'board') state: it isn't
a SysBus device, but inherits from the MachineState type.
Correct the instance size.
Doing so we avoid leaking an OpenTitanState pointer in
opentitan_machine_init().
Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-6-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 3 ++-
hw/riscv/opentitan.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 806ff73528..609473d07b 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -55,10 +55,11 @@ struct LowRISCIbexSoCState {
};
#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
+OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE)
typedef struct OpenTitanState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
LowRISCIbexSoCState soc;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 9535308197..6a2fcc4ade 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -78,8 +78,8 @@ static const MemMapEntry ibex_memmap[] = {
static void opentitan_machine_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
+ OpenTitanState *s = OPENTITAN_MACHINE(machine);
const MemMapEntry *memmap = ibex_memmap;
- OpenTitanState *s = g_new0(OpenTitanState, 1);
MemoryRegion *sys_mem = get_system_memory();
if (machine->ram_size != mc->default_ram_size) {
@@ -330,6 +330,7 @@ static const TypeInfo open_titan_types[] = {
}, {
.name = TYPE_OPENTITAN_MACHINE,
.parent = TYPE_MACHINE,
+ .instance_size = sizeof(OpenTitanState),
.class_init = opentitan_machine_class_init,
}
};
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (29 preceding siblings ...)
2023-06-14 1:19 ` [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address Alistair Francis
` (30 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Yin Wang, Alistair Francis, Daniel Henrique Barboza,
LIU Zhiwei, Weiwei Li
From: Yin Wang <yin.wang@intel.com>
Command "qemu-system-riscv64 -machine virt
-m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
would trigger this problem.Backtrace with:
#0 0x0000555555b5b1a4 in riscv_numa_get_default_cpu_node_id at ../hw/riscv/numa.c:211
#1 0x00005555558ce510 in machine_numa_finish_cpu_init at ../hw/core/machine.c:1230
#2 0x00005555558ce9d3 in machine_run_board_init at ../hw/core/machine.c:1346
#3 0x0000555555aaedc3 in qemu_init_board at ../softmmu/vl.c:2513
#4 0x0000555555aaf064 in qmp_x_exit_preconfig at ../softmmu/vl.c:2609
#5 0x0000555555ab1916 in qemu_init at ../softmmu/vl.c:3617
#6 0x000055555585463b in main at ../softmmu/main.c:47
This commit fixes the issue by adding parameter checks.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Yin Wang <yin.wang@intel.com>
Message-Id: <20230519023758.1759434-1-yin.wang@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/numa.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c
index 4720102561..e0414d5b1b 100644
--- a/hw/riscv/numa.c
+++ b/hw/riscv/numa.c
@@ -207,6 +207,12 @@ int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx)
{
int64_t nidx = 0;
+ if (ms->numa_state->num_nodes > ms->smp.cpus) {
+ error_report("Number of NUMA nodes (%d)"
+ " cannot exceed the number of available CPUs (%d).",
+ ms->numa_state->num_nodes, ms->smp.max_cpus);
+ exit(EXIT_FAILURE);
+ }
if (ms->numa_state->num_nodes) {
nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
if (ms->numa_state->num_nodes <= nidx) {
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (30 preceding siblings ...)
2023-06-14 1:19 ` [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes Alistair Francis
` (29 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
actual_address = (requested_address & ~mpmmask) | mpmbase.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230524015933.17349-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8e6c99e573..7505f9470a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -169,7 +169,7 @@ static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc,
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
- return (addr & env->cur_pmmask) | env->cur_pmbase;
+ return (addr & ~env->cur_pmmask) | env->cur_pmbase;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (31 preceding siblings ...)
2023-06-14 1:19 ` [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 34/60] target/riscv: smstateen check for fcsr Alistair Francis
` (28 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
write_mstatus() can only change current xl when in debug mode.
And we need update cur_pmmask/base in this case.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230524015933.17349-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cf7da4f87f..ad73691878 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1324,8 +1324,15 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
}
env->mstatus = mstatus;
- env->xl = cpu_recompute_xl(env);
+ /*
+ * Except in debug mode, UXL/SXL can only be modified by higher
+ * privilege mode. So xl will not be changed in normal mode.
+ */
+ if (env->debugger) {
+ env->xl = cpu_recompute_xl(env);
+ riscv_cpu_update_mask(env);
+ }
return RISCV_EXCP_NONE;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 34/60] target/riscv: smstateen check for fcsr
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (32 preceding siblings ...)
2023-06-14 1:19 ` [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 35/60] target/riscv: Reuse tb->flags.FS Alistair Francis
` (27 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Mayuresh Chitale, Weiwei Li, Alistair Francis
From: Mayuresh Chitale <mchitale@ventanamicro.com>
Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
and check for it when accessing the fcsr register and its fields.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230518175058.2772506-2-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ad73691878..58499b5afc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -82,6 +82,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
!riscv_cpu_cfg(env)->ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
+
+ if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+ return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
+ }
#endif
return RISCV_EXCP_NONE;
}
@@ -2104,6 +2108,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
return write_mstateen(env, csrno, wr_mask, new_val);
}
@@ -2177,6 +2184,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
+
return write_hstateen(env, csrno, wr_mask, new_val);
}
@@ -2263,6 +2274,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ if (!riscv_has_ext(env, RVF)) {
+ wr_mask |= SMSTATEEN0_FCSR;
+ }
+
return write_sstateen(env, csrno, wr_mask, new_val);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 35/60] target/riscv: Reuse tb->flags.FS
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (33 preceding siblings ...)
2023-06-14 1:19 ` [PULL 34/60] target/riscv: smstateen check for fcsr Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 36/60] target/riscv: smstateen knobs Alistair Francis
` (26 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mayuresh Chitale, Richard Henderson, Weiwei Li,
Alistair Francis
From: Mayuresh Chitale <mchitale@ventanamicro.com>
When misa.F is 0 tb->flags.FS field is unused and can be used to save
the current state of smstateen0.FCSR check which is needed by the
floating point translation routines.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230518175058.2772506-3-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 ++++++
target/riscv/insn_trans/trans_rvf.c.inc | 7 ++++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 35ddd0caac..523311b184 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -120,6 +120,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
}
+ /* With Zfinx, floating point is enabled/disabled by Smstateen. */
+ if (!riscv_has_ext(env, RVF)) {
+ fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE)
+ ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
+ }
+
if (cpu->cfg.debug && !icount_enabled()) {
flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index c47138575a..a0da7391c7 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -19,9 +19,10 @@
*/
#define REQUIRE_FPU do {\
- if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \
- if (!ctx->cfg_ptr->ext_zfinx) \
- return false; \
+ if (ctx->mstatus_fs == EXT_STATUS_DISABLED) { \
+ ctx->virt_inst_excp = ctx->virt_enabled && ctx->cfg_ptr->ext_zfinx; \
+ return false; \
+ } \
} while (0)
#define REQUIRE_ZFINX_OR_F(ctx) do {\
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 36/60] target/riscv: smstateen knobs
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (34 preceding siblings ...)
2023-06-14 1:19 ` [PULL 35/60] target/riscv: Reuse tb->flags.FS Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer Alistair Francis
` (25 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Mayuresh Chitale, Weiwei Li, Alistair Francis
From: Mayuresh Chitale <mchitale@ventanamicro.com>
Add knobs to allow users to enable smstateen and also export it via the
ISA extension string.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230518175058.2772506-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e67c78f860..d23b4c4d16 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
@@ -1601,8 +1602,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
-
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (35 preceding siblings ...)
2023-06-14 1:19 ` [PULL 36/60] target/riscv: smstateen knobs Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Alistair Francis
` (24 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/disas/dis-asm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index 2f6f91c2ee..2324f6b1a4 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -397,7 +397,7 @@ typedef struct disassemble_info {
char * disassembler_options;
/* Field intended to be used by targets in any way they deem suitable. */
- int64_t target_info;
+ void *target_info;
/* Options for Capstone disassembly. */
int cap_arch;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (36 preceding siblings ...)
2023-06-14 1:19 ` [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Alistair Francis
` (23 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Alistair Francis,
Daniel Henrique Barboza
From: Weiwei Li <liweiwei@iscas.ac.cn>
Split RISCVCPUConfig declarations to prepare for passing it to disas.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230523093539.203909-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 114 +---------------------------------
target/riscv/cpu_cfg.h | 136 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 137 insertions(+), 113 deletions(-)
create mode 100644 target/riscv/cpu_cfg.h
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1f39edc687..e3e08d315f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "qemu/int128.h"
#include "cpu_bits.h"
+#include "cpu_cfg.h"
#include "qapi/qapi-types-common.h"
#include "cpu-qom.h"
@@ -370,119 +371,6 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
-/*
- * map is a 16-bit bitmap: the most significant set bit in map is the maximum
- * satp mode that is supported. It may be chosen by the user and must respect
- * what qemu implements (valid_1_10_32/64) and what the hw is capable of
- * (supported bitmap below).
- *
- * init is a 16-bit bitmap used to make sure the user selected a correct
- * configuration as per the specification.
- *
- * supported is a 16-bit bitmap used to reflect the hw capabilities.
- */
-typedef struct {
- uint16_t map, init, supported;
-} RISCVSATPMap;
-
-struct RISCVCPUConfig {
- bool ext_zba;
- bool ext_zbb;
- bool ext_zbc;
- bool ext_zbkb;
- bool ext_zbkc;
- bool ext_zbkx;
- bool ext_zbs;
- bool ext_zca;
- bool ext_zcb;
- bool ext_zcd;
- bool ext_zce;
- bool ext_zcf;
- bool ext_zcmp;
- bool ext_zcmt;
- bool ext_zk;
- bool ext_zkn;
- bool ext_zknd;
- bool ext_zkne;
- bool ext_zknh;
- bool ext_zkr;
- bool ext_zks;
- bool ext_zksed;
- bool ext_zksh;
- bool ext_zkt;
- bool ext_ifencei;
- bool ext_icsr;
- bool ext_icbom;
- bool ext_icboz;
- bool ext_zicond;
- bool ext_zihintpause;
- bool ext_smstateen;
- bool ext_sstc;
- bool ext_svadu;
- bool ext_svinval;
- bool ext_svnapot;
- bool ext_svpbmt;
- bool ext_zdinx;
- bool ext_zawrs;
- bool ext_zfh;
- bool ext_zfhmin;
- bool ext_zfinx;
- bool ext_zhinx;
- bool ext_zhinxmin;
- bool ext_zve32f;
- bool ext_zve64f;
- bool ext_zve64d;
- bool ext_zmmul;
- bool ext_zvfh;
- bool ext_zvfhmin;
- bool ext_smaia;
- bool ext_ssaia;
- bool ext_sscofpmf;
- bool rvv_ta_all_1s;
- bool rvv_ma_all_1s;
-
- uint32_t mvendorid;
- uint64_t marchid;
- uint64_t mimpid;
-
- /* Vendor-specific custom extensions */
- bool ext_xtheadba;
- bool ext_xtheadbb;
- bool ext_xtheadbs;
- bool ext_xtheadcmo;
- bool ext_xtheadcondmov;
- bool ext_xtheadfmemidx;
- bool ext_xtheadfmv;
- bool ext_xtheadmac;
- bool ext_xtheadmemidx;
- bool ext_xtheadmempair;
- bool ext_xtheadsync;
- bool ext_XVentanaCondOps;
-
- uint8_t pmu_num;
- char *priv_spec;
- char *user_spec;
- char *bext_spec;
- char *vext_spec;
- uint16_t vlen;
- uint16_t elen;
- uint16_t cbom_blocksize;
- uint16_t cboz_blocksize;
- bool mmu;
- bool pmp;
- bool epmp;
- bool debug;
- bool misa_w;
-
- bool short_isa_string;
-
-#ifndef CONFIG_USER_ONLY
- RISCVSATPMap satp_mode;
-#endif
-};
-
-typedef struct RISCVCPUConfig RISCVCPUConfig;
-
/*
* RISCVCPU:
* @env: #CPURISCVState
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
new file mode 100644
index 0000000000..c4a627d335
--- /dev/null
+++ b/target/riscv/cpu_cfg.h
@@ -0,0 +1,136 @@
+/*
+ * QEMU RISC-V CPU CFG
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ * Copyright (c) 2021-2023 PLCT Lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_CPU_CFG_H
+#define RISCV_CPU_CFG_H
+
+/*
+ * map is a 16-bit bitmap: the most significant set bit in map is the maximum
+ * satp mode that is supported. It may be chosen by the user and must respect
+ * what qemu implements (valid_1_10_32/64) and what the hw is capable of
+ * (supported bitmap below).
+ *
+ * init is a 16-bit bitmap used to make sure the user selected a correct
+ * configuration as per the specification.
+ *
+ * supported is a 16-bit bitmap used to reflect the hw capabilities.
+ */
+typedef struct {
+ uint16_t map, init, supported;
+} RISCVSATPMap;
+
+struct RISCVCPUConfig {
+ bool ext_zba;
+ bool ext_zbb;
+ bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
+ bool ext_zbs;
+ bool ext_zca;
+ bool ext_zcb;
+ bool ext_zcd;
+ bool ext_zce;
+ bool ext_zcf;
+ bool ext_zcmp;
+ bool ext_zcmt;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
+ bool ext_ifencei;
+ bool ext_icsr;
+ bool ext_icbom;
+ bool ext_icboz;
+ bool ext_zicond;
+ bool ext_zihintpause;
+ bool ext_smstateen;
+ bool ext_sstc;
+ bool ext_svadu;
+ bool ext_svinval;
+ bool ext_svnapot;
+ bool ext_svpbmt;
+ bool ext_zdinx;
+ bool ext_zawrs;
+ bool ext_zfh;
+ bool ext_zfhmin;
+ bool ext_zfinx;
+ bool ext_zhinx;
+ bool ext_zhinxmin;
+ bool ext_zve32f;
+ bool ext_zve64f;
+ bool ext_zve64d;
+ bool ext_zmmul;
+ bool ext_zvfh;
+ bool ext_zvfhmin;
+ bool ext_smaia;
+ bool ext_ssaia;
+ bool ext_sscofpmf;
+ bool rvv_ta_all_1s;
+ bool rvv_ma_all_1s;
+
+ uint32_t mvendorid;
+ uint64_t marchid;
+ uint64_t mimpid;
+
+ /* Vendor-specific custom extensions */
+ bool ext_xtheadba;
+ bool ext_xtheadbb;
+ bool ext_xtheadbs;
+ bool ext_xtheadcmo;
+ bool ext_xtheadcondmov;
+ bool ext_xtheadfmemidx;
+ bool ext_xtheadfmv;
+ bool ext_xtheadmac;
+ bool ext_xtheadmemidx;
+ bool ext_xtheadmempair;
+ bool ext_xtheadsync;
+ bool ext_XVentanaCondOps;
+
+ uint8_t pmu_num;
+ char *priv_spec;
+ char *user_spec;
+ char *bext_spec;
+ char *vext_spec;
+ uint16_t vlen;
+ uint16_t elen;
+ uint16_t cbom_blocksize;
+ uint16_t cboz_blocksize;
+ bool mmu;
+ bool pmp;
+ bool epmp;
+ bool debug;
+ bool misa_w;
+
+ bool short_isa_string;
+
+#ifndef CONFIG_USER_ONLY
+ RISCVSATPMap satp_mode;
+#endif
+};
+
+typedef struct RISCVCPUConfig RISCVCPUConfig;
+#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (37 preceding siblings ...)
2023-06-14 1:19 ` [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
` (22 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 10 +++++++---
target/riscv/cpu.c | 1 +
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index d597161d46..f2dd5fd531 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "disas/dis-asm.h"
-
+#include "target/riscv/cpu_cfg.h"
/* types */
@@ -969,6 +969,7 @@ typedef enum {
/* structures */
typedef struct {
+ RISCVCPUConfig *cfg;
uint64_t pc;
uint64_t inst;
int32_t imm;
@@ -4861,11 +4862,13 @@ static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
/* disassemble instruction */
static void
-disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
+disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
+ RISCVCPUConfig *cfg)
{
rv_decode dec = { 0 };
dec.pc = pc;
dec.inst = inst;
+ dec.cfg = cfg;
decode_inst_opcode(&dec, isa);
decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
@@ -4920,7 +4923,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
break;
}
- disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
+ disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
+ (RISCVCPUConfig *)info->target_info);
(*info->fprintf_func)(info->stream, "%s", buf);
return len;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d23b4c4d16..938c7bd87b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -849,6 +849,7 @@ static void riscv_cpu_reset_hold(Object *obj)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
RISCVCPU *cpu = RISCV_CPU(s);
+ info->target_info = &cpu->cfg;
switch (riscv_cpu_mxl(&cpu->env)) {
case MXL_RV32:
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (38 preceding siblings ...)
2023-06-14 1:19 ` [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions Alistair Francis
` (21 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index f2dd5fd531..6659f92179 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2505,7 +2505,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
- if (((inst >> 12) & 0b01)) {
+ if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
switch ((inst >> 8) & 0b01111) {
case 8:
if (((inst >> 4) & 0b01111) >= 4) {
@@ -2531,6 +2531,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
} else {
switch ((inst >> 10) & 0b011) {
case 0:
+ if (!dec->cfg->ext_zcmt) {
+ break;
+ }
if (((inst >> 2) & 0xFF) >= 32) {
op = rv_op_cm_jalt;
} else {
@@ -2538,6 +2541,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 3:
+ if (!dec->cfg->ext_zcmp) {
+ break;
+ }
switch ((inst >> 5) & 0b011) {
case 1: op = rv_op_cm_mvsa01; break;
case 3: op = rv_op_cm_mva01s; break;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (39 preceding siblings ...)
2023-06-14 1:19 ` [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:19 ` [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Alistair Francis
` (20 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 6659f92179..c9a81af662 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4598,16 +4598,24 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
append(buf, rv_ireg_name_sym[dec->rs2], buflen);
break;
case '3':
- append(buf, rv_freg_name_sym[dec->rd], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
+ rv_freg_name_sym[dec->rd],
+ buflen);
break;
case '4':
- append(buf, rv_freg_name_sym[dec->rs1], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
+ rv_freg_name_sym[dec->rs1],
+ buflen);
break;
case '5':
- append(buf, rv_freg_name_sym[dec->rs2], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
+ rv_freg_name_sym[dec->rs2],
+ buflen);
break;
case '6':
- append(buf, rv_freg_name_sym[dec->rs3], buflen);
+ append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
+ rv_freg_name_sym[dec->rs3],
+ buflen);
break;
case '7':
snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (40 preceding siblings ...)
2023-06-14 1:19 ` [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions Alistair Francis
@ 2023-06-14 1:19 ` Alistair Francis
2023-06-14 1:20 ` [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters Alistair Francis
` (19 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:19 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
instructions are the same op index as their own. And they have no
functional decomp_data. So they have no functional difference from just
leaving them as zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 740 +++++++++++++++++++++++++-------------------------
1 file changed, 370 insertions(+), 370 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index c9a81af662..806c4b6f93 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1732,376 +1732,376 @@ const rv_opcode_data opcode_data[] = {
{ "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 },
- { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 },
- { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 },
- { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 },
- { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 },
- { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 },
- { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 },
- { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 },
- { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 },
- { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 },
- { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 },
- { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 },
- { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 },
- { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 },
- { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 },
- { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 },
- { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 },
- { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 },
- { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 },
- { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 },
- { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 },
- { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 },
- { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 },
- { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 },
- { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 },
- { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 },
- { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 },
- { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 },
- { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 },
- { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 },
- { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 },
- { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 },
- { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 },
- { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 },
- { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 },
- { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 },
- { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 },
- { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 },
- { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 },
- { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 },
- { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 },
- { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 },
- { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 },
- { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 },
- { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 },
- { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 },
- { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 },
- { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 },
- { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 },
- { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 },
- { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 },
- { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 },
- { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 },
- { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 },
- { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 },
- { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 },
- { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 },
- { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 },
- { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 },
- { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 },
- { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 },
- { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 },
- { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 },
- { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 },
- { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 },
- { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 },
- { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 },
- { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 },
- { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 },
- { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 },
- { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 },
- { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 },
- { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 },
- { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 },
- { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 },
- { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 },
- { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 },
- { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 },
- { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 },
- { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 },
- { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 },
- { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 },
- { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 },
- { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 },
- { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 },
- { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 },
- { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 },
- { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 },
- { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 },
- { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 },
- { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 },
- { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 },
- { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 },
- { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 },
- { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 },
- { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 },
- { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 },
- { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 },
- { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 },
- { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 },
- { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 },
- { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 },
- { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 },
- { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 },
- { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 },
- { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 },
- { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 },
- { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 },
- { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 },
- { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 },
- { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 },
- { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 },
- { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 },
- { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 },
- { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 },
- { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 },
- { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 },
- { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 },
- { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 },
- { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 },
- { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 },
- { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 },
- { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 },
- { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 },
- { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 },
- { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 },
- { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 },
- { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 },
- { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 },
- { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 },
- { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 },
- { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 },
- { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 },
- { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 },
- { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 },
- { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 },
- { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 },
- { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 },
- { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 },
- { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 },
- { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 },
- { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 },
- { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 },
- { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 },
- { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 },
- { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 },
- { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 },
- { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 },
- { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 },
- { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 },
- { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 },
- { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 },
- { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 },
- { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 },
- { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 },
- { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 },
- { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 },
- { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 },
- { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 },
- { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 },
- { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 },
- { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 },
- { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 },
- { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 },
- { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 },
- { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 },
- { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 },
- { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 },
- { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 },
- { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 },
- { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 },
- { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 },
- { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 },
- { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 },
- { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 },
- { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 },
- { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 },
- { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 },
- { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 },
- { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 },
- { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 },
- { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 },
- { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 },
- { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 },
- { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 },
- { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 },
- { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 },
- { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 },
- { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 },
- { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 },
- { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 },
- { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 },
- { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 },
- { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 },
- { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 },
- { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 },
- { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 },
- { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 },
- { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 },
- { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 },
- { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 },
- { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 },
- { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 },
- { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 },
- { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 },
- { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 },
- { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 },
- { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 },
- { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 },
- { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 },
- { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 },
- { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 },
- { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 },
- { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 },
- { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 },
- { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 },
- { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 },
- { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 },
- { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 },
- { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 },
- { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 },
- { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 },
- { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 },
- { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 },
- { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 },
- { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 },
- { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 },
- { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 },
- { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 },
- { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 },
- { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 },
- { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 },
- { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 },
- { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 },
- { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 },
- { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 },
- { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 },
- { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 },
- { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 },
- { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 },
- { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 },
- { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 },
- { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 },
- { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 },
- { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 },
- { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 },
- { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 },
- { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 },
- { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 },
- { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 },
- { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 },
- { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 },
- { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 },
- { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 },
- { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 },
- { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 },
- { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 },
- { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 },
- { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 },
- { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 },
- { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 },
- { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 },
- { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 },
- { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 },
- { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 },
- { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 },
- { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 },
- { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 },
- { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 },
- { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 },
- { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 },
- { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 },
- { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 },
- { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 },
- { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 },
- { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 },
- { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 },
- { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 },
- { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 },
- { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 },
- { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 },
- { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 },
- { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 },
- { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 },
- { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 },
- { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 },
- { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 },
- { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 },
- { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 },
- { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 },
- { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 },
- { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 },
- { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 },
- { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 },
- { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 },
- { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 },
- { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 },
- { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 },
- { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 },
- { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 },
- { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 },
- { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 },
- { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 },
- { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 },
- { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 },
- { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 },
- { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 },
- { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 },
- { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 },
- { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 },
- { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 },
- { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 },
- { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 },
- { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 },
- { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 },
- { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 },
- { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 },
- { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 },
- { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 },
- { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 },
- { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 },
- { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 },
- { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 },
- { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 },
- { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 },
- { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 },
- { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 },
- { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 },
- { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 },
- { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 },
- { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 },
- { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 },
- { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 },
- { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 },
- { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 },
- { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 },
- { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 },
- { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 },
- { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 },
- { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 },
- { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 },
- { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 },
- { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 },
- { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 },
- { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 },
- { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 },
- { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 },
- { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 },
- { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 },
- { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 },
- { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 },
- { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 },
- { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 },
- { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 },
- { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 },
- { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 },
- { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 },
- { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 },
- { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 },
- { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 },
- { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 },
- { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 },
- { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 },
- { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 },
- { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 },
- { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 },
- { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
- { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
- { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
- { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 },
+ { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, 0, 0, 0 },
+ { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, 0, 0, 0 },
+ { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
+ { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
+ { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, 0, 0, 0 },
+ { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
+ { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, 0, 0, 0 },
+ { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, 0, 0, 0 },
+ { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, 0, 0, 0 },
+ { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, 0, 0, 0 },
+ { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, 0, 0, 0 },
+ { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, 0, 0, 0 },
+ { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, 0, 0, 0 },
+ { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, 0, 0, 0 },
+ { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
+ { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
+ { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, 0, 0, 0 },
+ { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, 0, 0, 0 },
+ { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, 0, 0, 0 },
+ { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, 0, 0, 0 },
+ { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, 0, 0, 0 },
+ { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, 0, 0, 0 },
+ { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
+ { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
+ { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
+ { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
+ { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
+ { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
+ { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, 0, 0, 0 },
+ { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, 0, 0, 0 },
+ { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
{ "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (41 preceding siblings ...)
2023-06-14 1:19 ` [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 44/60] disas/riscv.c: Remove redundant parentheses Alistair Francis
` (18 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Fix lines with over 80 characters.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 201 +++++++++++++++++++++++++++++++++++---------------
1 file changed, 140 insertions(+), 61 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 806c4b6f93..bc433c4120 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1110,8 +1110,10 @@ static const char rv_vreg_name_sym[32][4] = {
/* pseudo-instruction constraints */
static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
-static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
+static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero,
+ rvc_end };
+static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0,
+ rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
@@ -1141,18 +1143,28 @@ static const rvc_constraint rvcc_bleu[] = { rvc_end };
static const rvc_constraint rvcc_bgt[] = { rvc_end };
static const rvc_constraint rvcc_bgtu[] = { rvc_end };
static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
-static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
-static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
-static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
-static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
-static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
-static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
-static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
+static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra,
+ rvc_end };
+static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
+ rvc_end };
+static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00,
+ rvc_end };
+static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01,
+ rvc_end };
+static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0,
+ rvc_csr_eq_0xc02, rvc_end };
+static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0,
+ rvc_csr_eq_0xc80, rvc_end };
+static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81,
+ rvc_end };
static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
rvc_csr_eq_0xc82, rvc_end };
-static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
-static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
-static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
+static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003,
+ rvc_end };
+static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002,
+ rvc_end };
+static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001,
+ rvc_end };
static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
@@ -1554,17 +1566,23 @@ const rv_opcode_data opcode_data[] = {
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
{ "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
- { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
- { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
+ { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
+ rv_op_fld, 0 },
+ { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw,
+ rv_op_lw },
{ "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
- { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
+ { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
+ rv_op_fsd, 0 },
+ { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw,
+ rv_op_sw },
{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
{ "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
rv_op_addi, rvcd_imm_nz },
{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
- { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
@@ -1575,37 +1593,63 @@ const rv_opcode_data opcode_data[] = {
rv_op_srai, rv_op_srai, rvcd_imm_nz },
{ "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
rv_op_andi, rv_op_andi },
- { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
- { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
- { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
- { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
- { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
- { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
- { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
- { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
- { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
+ { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub,
+ rv_op_sub },
+ { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor,
+ rv_op_xor },
+ { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or,
+ rv_op_or },
+ { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and,
+ rv_op_and },
+ { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw,
+ rv_op_subw },
+ { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw,
+ rv_op_addw },
+ { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal,
+ rv_op_jal },
+ { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq,
+ rv_op_beq },
+ { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne,
+ rv_op_bne },
{ "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
rv_op_slli, rv_op_slli, rvcd_imm_nz },
- { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
- { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
- { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
- { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
- { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
- { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
- { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
- { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
- { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
- { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
- { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
- { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
- { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
- { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
- { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
- { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
+ { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld,
+ rv_op_fld, rv_op_fld },
+ { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
+ rv_op_lw, rv_op_lw },
+ { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0,
+ 0 },
+ { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
+ rv_op_jalr, rv_op_jalr },
+ { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi,
+ rv_op_addi },
+ { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
+ rv_op_ebreak, rv_op_ebreak },
+ { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr,
+ rv_op_jalr, rv_op_jalr },
+ { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add,
+ rv_op_add },
+ { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd,
+ rv_op_fsd, rv_op_fsd },
+ { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
+ rv_op_sw, rv_op_sw },
+ { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0,
+ 0 },
+ { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
+ rv_op_ld },
+ { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
+ rv_op_sd },
+ { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw,
+ rv_op_addiw },
+ { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld,
+ rv_op_ld },
+ { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd,
+ rv_op_sd },
{ "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
{ "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
{ "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
- { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
+ { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
+ rv_op_sq },
{ "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
{ "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
@@ -2844,7 +2888,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 11:
- switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 24) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 2: op = rv_op_amoadd_w; break;
case 3: op = rv_op_amoadd_d; break;
case 4: op = rv_op_amoadd_q; break;
@@ -2893,7 +2938,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 12:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_add; break;
case 1: op = rv_op_sll; break;
case 2: op = rv_op_slt; break;
@@ -2966,7 +3012,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 13: op = rv_op_lui; break;
case 14:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addw; break;
case 1: op = rv_op_sllw; break;
case 5: op = rv_op_srlw; break;
@@ -3175,35 +3222,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 112:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_s; break;
case 1: op = rv_op_fclass_s; break;
}
break;
case 113:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_d; break;
case 1: op = rv_op_fclass_d; break;
}
break;
case 115:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_q; break;
case 1: op = rv_op_fclass_q; break;
}
break;
case 120:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_s_x; break;
}
break;
case 121:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_d_x; break;
}
break;
case 123:
- switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
+ switch (((inst >> 17) & 0b11111000) |
+ ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_q_x; break;
}
break;
@@ -3224,9 +3277,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 11: op = rv_op_vxor_vv; break;
case 12: op = rv_op_vrgather_vv; break;
case 14: op = rv_op_vrgatherei16_vv; break;
- case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vvm;
+ }
+ break;
case 17: op = rv_op_vmadc_vvm; break;
- case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
+ case 18:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vsbc_vvm;
+ }
+ break;
case 19: op = rv_op_vmsbc_vvm; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
@@ -3373,7 +3434,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 2: op = rv_op_vmsof_m; break;
case 3: op = rv_op_vmsif_m; break;
case 16: op = rv_op_viota_m; break;
- case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
+ case 17:
+ if (((inst >> 20) & 0b11111) == 0) {
+ op = rv_op_vid_v;
+ }
+ break;
}
break;
case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
@@ -3423,7 +3488,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 12: op = rv_op_vrgather_vi; break;
case 14: op = rv_op_vslideup_vi; break;
case 15: op = rv_op_vslidedown_vi; break;
- case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vim;
+ }
+ break;
case 17: op = rv_op_vmadc_vim; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
@@ -3473,9 +3542,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 12: op = rv_op_vrgather_vx; break;
case 14: op = rv_op_vslideup_vx; break;
case 15: op = rv_op_vslidedown_vx; break;
- case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
+ case 16:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vadc_vxm;
+ }
+ break;
case 17: op = rv_op_vmadc_vxm; break;
- case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
+ case 18:
+ if (((inst >> 25) & 1) == 0) {
+ op = rv_op_vsbc_vxm;
+ }
+ break;
case 19: op = rv_op_vmsbc_vxm; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
@@ -3646,7 +3723,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 28:
switch (((inst >> 12) & 0b111)) {
case 0:
- switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
+ switch (((inst >> 20) & 0b111111100000) |
+ ((inst >> 7) & 0b000000011111)) {
case 0:
switch (((inst >> 15) & 0b1111111111)) {
case 0: op = rv_op_ecall; break;
@@ -3696,7 +3774,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 30:
- switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
+ switch (((inst >> 22) & 0b1111111000) |
+ ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addd; break;
case 1: op = rv_op_slld; break;
case 5: op = rv_op_srld; break;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 44/60] disas/riscv.c: Remove redundant parentheses
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (42 preceding siblings ...)
2023-06-14 1:20 ` [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 45/60] target/riscv: Fix target address to update badaddr Alistair Francis
` (17 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Daniel Henrique Barboza,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 219 +++++++++++++++++++++++++-------------------------
1 file changed, 110 insertions(+), 109 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index bc433c4120..5005364aba 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2390,9 +2390,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
- switch (((inst >> 0) & 0b11)) {
+ switch ((inst >> 0) & 0b11) {
case 0:
- switch (((inst >> 13) & 0b111)) {
+ switch ((inst >> 13) & 0b111) {
case 0: op = rv_op_c_addi4spn; break;
case 1:
if (isa == rv128) {
@@ -2445,9 +2445,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 1:
- switch (((inst >> 13) & 0b111)) {
+ switch ((inst >> 13) & 0b111) {
case 0:
- switch (((inst >> 2) & 0b11111111111)) {
+ switch ((inst >> 2) & 0b11111111111) {
case 0: op = rv_op_c_nop; break;
default: op = rv_op_c_addi; break;
}
@@ -2461,13 +2461,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 2: op = rv_op_c_li; break;
case 3:
- switch (((inst >> 7) & 0b11111)) {
+ switch ((inst >> 7) & 0b11111) {
case 2: op = rv_op_c_addi16sp; break;
default: op = rv_op_c_lui; break;
}
break;
case 4:
- switch (((inst >> 10) & 0b11)) {
+ switch ((inst >> 10) & 0b11) {
case 0:
op = rv_op_c_srli;
break;
@@ -2504,7 +2504,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 2:
- switch (((inst >> 13) & 0b111)) {
+ switch ((inst >> 13) & 0b111) {
case 0:
op = rv_op_c_slli;
break;
@@ -2524,17 +2524,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 4:
- switch (((inst >> 12) & 0b1)) {
+ switch ((inst >> 12) & 0b1) {
case 0:
- switch (((inst >> 2) & 0b11111)) {
+ switch ((inst >> 2) & 0b11111) {
case 0: op = rv_op_c_jr; break;
default: op = rv_op_c_mv; break;
}
break;
case 1:
- switch (((inst >> 2) & 0b11111)) {
+ switch ((inst >> 2) & 0b11111) {
case 0:
- switch (((inst >> 7) & 0b11111)) {
+ switch ((inst >> 7) & 0b11111) {
case 0: op = rv_op_c_ebreak; break;
default: op = rv_op_c_jalr; break;
}
@@ -2608,9 +2608,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 3:
- switch (((inst >> 2) & 0b11111)) {
+ switch ((inst >> 2) & 0b11111) {
case 0:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_lb; break;
case 1: op = rv_op_lh; break;
case 2: op = rv_op_lw; break;
@@ -2622,17 +2622,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 1:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b111111111111)) {
+ switch ((inst >> 20) & 0b111111111111) {
case 40: op = rv_op_vl1re8_v; break;
case 552: op = rv_op_vl2re8_v; break;
case 1576: op = rv_op_vl4re8_v; break;
case 3624: op = rv_op_vl8re8_v; break;
}
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vle8_v; break;
case 11: op = rv_op_vlm_v; break;
case 16: op = rv_op_vle8ff_v; break;
@@ -2647,15 +2647,15 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_fld; break;
case 4: op = rv_op_flq; break;
case 5:
- switch (((inst >> 20) & 0b111111111111)) {
+ switch ((inst >> 20) & 0b111111111111) {
case 40: op = rv_op_vl1re16_v; break;
case 552: op = rv_op_vl2re16_v; break;
case 1576: op = rv_op_vl4re16_v; break;
case 3624: op = rv_op_vl8re16_v; break;
}
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vle16_v; break;
case 16: op = rv_op_vle16ff_v; break;
}
@@ -2666,15 +2666,15 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 6:
- switch (((inst >> 20) & 0b111111111111)) {
+ switch ((inst >> 20) & 0b111111111111) {
case 40: op = rv_op_vl1re32_v; break;
case 552: op = rv_op_vl2re32_v; break;
case 1576: op = rv_op_vl4re32_v; break;
case 3624: op = rv_op_vl8re32_v; break;
}
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vle32_v; break;
case 16: op = rv_op_vle32ff_v; break;
}
@@ -2685,15 +2685,15 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 7:
- switch (((inst >> 20) & 0b111111111111)) {
+ switch ((inst >> 20) & 0b111111111111) {
case 40: op = rv_op_vl1re64_v; break;
case 552: op = rv_op_vl2re64_v; break;
case 1576: op = rv_op_vl4re64_v; break;
case 3624: op = rv_op_vl8re64_v; break;
}
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vle64_v; break;
case 16: op = rv_op_vle64ff_v; break;
}
@@ -2706,25 +2706,25 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 3:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fence; break;
case 1: op = rv_op_fence_i; break;
case 2: op = rv_op_lq; break;
}
break;
case 4:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addi; break;
case 1:
- switch (((inst >> 27) & 0b11111)) {
+ switch ((inst >> 27) & 0b11111) {
case 0b00000: op = rv_op_slli; break;
case 0b00001:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0001111: op = rv_op_zip; break;
}
break;
case 0b00010:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0000000: op = rv_op_sha256sum0; break;
case 0b0000001: op = rv_op_sha256sum1; break;
case 0b0000010: op = rv_op_sha256sig0; break;
@@ -2739,7 +2739,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 0b00101: op = rv_op_bseti; break;
case 0b00110:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0000000: op = rv_op_aes64im; break;
default:
if (((inst >> 24) & 0b0111) == 0b001) {
@@ -2751,7 +2751,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0000000: op = rv_op_clz; break;
case 0b0000001: op = rv_op_ctz; break;
case 0b0000010: op = rv_op_cpop; break;
@@ -2766,10 +2766,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_sltiu; break;
case 4: op = rv_op_xori; break;
case 5:
- switch (((inst >> 27) & 0b11111)) {
+ switch ((inst >> 27) & 0b11111) {
case 0b00000: op = rv_op_srli; break;
case 0b00001:
- switch (((inst >> 20) & 0b1111111)) {
+ switch ((inst >> 20) & 0b1111111) {
case 0b0001111: op = rv_op_unzip; break;
}
break;
@@ -2792,10 +2792,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 5: op = rv_op_auipc; break;
case 6:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addiw; break;
case 1:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_slliw; break;
case 2: op = rv_op_slli_uw; break;
case 24:
@@ -2808,7 +2808,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 5:
- switch (((inst >> 25) & 0b1111111)) {
+ switch ((inst >> 25) & 0b1111111) {
case 0: op = rv_op_srliw; break;
case 32: op = rv_op_sraiw; break;
case 48: op = rv_op_roriw; break;
@@ -2817,7 +2817,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 8:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_sb; break;
case 1: op = rv_op_sh; break;
case 2: op = rv_op_sw; break;
@@ -2826,17 +2826,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 9:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b111111111111)) {
+ switch ((inst >> 20) & 0b111111111111) {
case 40: op = rv_op_vs1r_v; break;
case 552: op = rv_op_vs2r_v; break;
case 1576: op = rv_op_vs4r_v; break;
case 3624: op = rv_op_vs8r_v; break;
}
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vse8_v; break;
case 11: op = rv_op_vsm_v; break;
}
@@ -2850,9 +2850,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_fsd; break;
case 4: op = rv_op_fsq; break;
case 5:
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vse16_v; break;
}
break;
@@ -2862,9 +2862,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 6:
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vse32_v; break;
}
break;
@@ -2874,9 +2874,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 7:
- switch (((inst >> 26) & 0b111)) {
+ switch ((inst >> 26) & 0b111) {
case 0:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_vse64_v; break;
}
break;
@@ -2897,17 +2897,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 11: op = rv_op_amoswap_d; break;
case 12: op = rv_op_amoswap_q; break;
case 18:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_lr_w; break;
}
break;
case 19:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_lr_d; break;
}
break;
case 20:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_lr_q; break;
}
break;
@@ -3039,35 +3039,35 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 16:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fmadd_s; break;
case 1: op = rv_op_fmadd_d; break;
case 3: op = rv_op_fmadd_q; break;
}
break;
case 17:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fmsub_s; break;
case 1: op = rv_op_fmsub_d; break;
case 3: op = rv_op_fmsub_q; break;
}
break;
case 18:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fnmsub_s; break;
case 1: op = rv_op_fnmsub_d; break;
case 3: op = rv_op_fnmsub_q; break;
}
break;
case 19:
- switch (((inst >> 25) & 0b11)) {
+ switch ((inst >> 25) & 0b11) {
case 0: op = rv_op_fnmadd_s; break;
case 1: op = rv_op_fnmadd_d; break;
case 3: op = rv_op_fnmadd_q; break;
}
break;
case 20:
- switch (((inst >> 25) & 0b1111111)) {
+ switch ((inst >> 25) & 0b1111111) {
case 0: op = rv_op_fadd_s; break;
case 1: op = rv_op_fadd_d; break;
case 3: op = rv_op_fadd_q; break;
@@ -3081,100 +3081,100 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 13: op = rv_op_fdiv_d; break;
case 15: op = rv_op_fdiv_q; break;
case 16:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fsgnj_s; break;
case 1: op = rv_op_fsgnjn_s; break;
case 2: op = rv_op_fsgnjx_s; break;
}
break;
case 17:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fsgnj_d; break;
case 1: op = rv_op_fsgnjn_d; break;
case 2: op = rv_op_fsgnjx_d; break;
}
break;
case 19:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fsgnj_q; break;
case 1: op = rv_op_fsgnjn_q; break;
case 2: op = rv_op_fsgnjx_q; break;
}
break;
case 20:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fmin_s; break;
case 1: op = rv_op_fmax_s; break;
}
break;
case 21:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fmin_d; break;
case 1: op = rv_op_fmax_d; break;
}
break;
case 23:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fmin_q; break;
case 1: op = rv_op_fmax_q; break;
}
break;
case 32:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 1: op = rv_op_fcvt_s_d; break;
case 3: op = rv_op_fcvt_s_q; break;
}
break;
case 33:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_d_s; break;
case 3: op = rv_op_fcvt_d_q; break;
}
break;
case 35:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_q_s; break;
case 1: op = rv_op_fcvt_q_d; break;
}
break;
case 44:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fsqrt_s; break;
}
break;
case 45:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fsqrt_d; break;
}
break;
case 47:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fsqrt_q; break;
}
break;
case 80:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fle_s; break;
case 1: op = rv_op_flt_s; break;
case 2: op = rv_op_feq_s; break;
}
break;
case 81:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fle_d; break;
case 1: op = rv_op_flt_d; break;
case 2: op = rv_op_feq_d; break;
}
break;
case 83:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_fle_q; break;
case 1: op = rv_op_flt_q; break;
case 2: op = rv_op_feq_q; break;
}
break;
case 96:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_w_s; break;
case 1: op = rv_op_fcvt_wu_s; break;
case 2: op = rv_op_fcvt_l_s; break;
@@ -3182,7 +3182,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 97:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_w_d; break;
case 1: op = rv_op_fcvt_wu_d; break;
case 2: op = rv_op_fcvt_l_d; break;
@@ -3190,7 +3190,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 99:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_w_q; break;
case 1: op = rv_op_fcvt_wu_q; break;
case 2: op = rv_op_fcvt_l_q; break;
@@ -3198,7 +3198,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 104:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_s_w; break;
case 1: op = rv_op_fcvt_s_wu; break;
case 2: op = rv_op_fcvt_s_l; break;
@@ -3206,7 +3206,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 105:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_d_w; break;
case 1: op = rv_op_fcvt_d_wu; break;
case 2: op = rv_op_fcvt_d_l; break;
@@ -3214,7 +3214,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 107:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_fcvt_q_w; break;
case 1: op = rv_op_fcvt_q_wu; break;
case 2: op = rv_op_fcvt_q_l; break;
@@ -3263,9 +3263,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 21:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vv; break;
case 2: op = rv_op_vsub_vv; break;
case 4: op = rv_op_vminu_vv; break;
@@ -3320,7 +3320,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 1:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vfadd_vv; break;
case 1: op = rv_op_vfredusum_vs; break;
case 2: op = rv_op_vfsub_vv; break;
@@ -3333,12 +3333,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 9: op = rv_op_vfsgnjn_vv; break;
case 10: op = rv_op_vfsgnjx_vv; break;
case 16:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
}
break;
case 18:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_vfcvt_xu_f_v; break;
case 1: op = rv_op_vfcvt_x_f_v; break;
case 2: op = rv_op_vfcvt_f_xu_v; break;
@@ -3363,7 +3363,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 19:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_vfsqrt_v; break;
case 4: op = rv_op_vfrsqrt7_v; break;
case 5: op = rv_op_vfrec7_v; break;
@@ -3398,7 +3398,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 2:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vredsum_vs; break;
case 1: op = rv_op_vredand_vs; break;
case 2: op = rv_op_vredor_vs; break;
@@ -3412,14 +3412,14 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 10: op = rv_op_vasubu_vv; break;
case 11: op = rv_op_vasub_vv; break;
case 16:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
case 16: op = rv_op_vcpop_m; break;
case 17: op = rv_op_vfirst_m; break;
}
break;
case 18:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 2: op = rv_op_vzext_vf8; break;
case 3: op = rv_op_vsext_vf8; break;
case 4: op = rv_op_vzext_vf4; break;
@@ -3429,7 +3429,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 20:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 1: op = rv_op_vmsbf_m; break;
case 2: op = rv_op_vmsof_m; break;
case 3: op = rv_op_vmsif_m; break;
@@ -3479,7 +3479,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 3:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vi; break;
case 3: op = rv_op_vrsub_vi; break;
case 9: op = rv_op_vand_vi; break;
@@ -3510,7 +3510,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 33: op = rv_op_vsadd_vi; break;
case 37: op = rv_op_vsll_vi; break;
case 39:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_vmv1r_v; break;
case 1: op = rv_op_vmv2r_v; break;
case 3: op = rv_op_vmv4r_v; break;
@@ -3528,7 +3528,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 4:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vx; break;
case 2: op = rv_op_vsub_vx; break;
case 3: op = rv_op_vrsub_vx; break;
@@ -3585,7 +3585,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 5:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vfadd_vf; break;
case 2: op = rv_op_vfsub_vf; break;
case 4: op = rv_op_vfmin_vf; break;
@@ -3596,7 +3596,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 14: op = rv_op_vfslide1up_vf; break;
case 15: op = rv_op_vfslide1down_vf; break;
case 16:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
}
break;
@@ -3636,7 +3636,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 6:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 8: op = rv_op_vaaddu_vx; break;
case 9: op = rv_op_vaadd_vx; break;
case 10: op = rv_op_vasubu_vx; break;
@@ -3644,7 +3644,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 14: op = rv_op_vslide1up_vx; break;
case 15: op = rv_op_vslide1down_vx; break;
case 16:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
}
break;
@@ -3689,15 +3689,15 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 22:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addid; break;
case 1:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_sllid; break;
}
break;
case 5:
- switch (((inst >> 26) & 0b111111)) {
+ switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_srlid; break;
case 16: op = rv_op_sraid; break;
}
@@ -3705,7 +3705,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 24:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_beq; break;
case 1: op = rv_op_bne; break;
case 4: op = rv_op_blt; break;
@@ -3715,33 +3715,33 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 25:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_jalr; break;
}
break;
case 27: op = rv_op_jal; break;
case 28:
- switch (((inst >> 12) & 0b111)) {
+ switch ((inst >> 12) & 0b111) {
case 0:
switch (((inst >> 20) & 0b111111100000) |
((inst >> 7) & 0b000000011111)) {
case 0:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 0: op = rv_op_ecall; break;
case 32: op = rv_op_ebreak; break;
case 64: op = rv_op_uret; break;
}
break;
case 256:
- switch (((inst >> 20) & 0b11111)) {
+ switch ((inst >> 20) & 0b11111) {
case 2:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_sret; break;
}
break;
case 4: op = rv_op_sfence_vm; break;
case 5:
- switch (((inst >> 15) & 0b11111)) {
+ switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_wfi; break;
}
break;
@@ -3749,17 +3749,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
break;
case 288: op = rv_op_sfence_vma; break;
case 512:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 64: op = rv_op_hret; break;
}
break;
case 768:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 64: op = rv_op_mret; break;
}
break;
case 1952:
- switch (((inst >> 15) & 0b1111111111)) {
+ switch ((inst >> 15) & 0b1111111111) {
case 576: op = rv_op_dret; break;
}
break;
@@ -4611,7 +4611,8 @@ static size_t inst_length(rv_inst inst)
{
/* NOTE: supports maximum instruction size of 64-bits */
- /* instruction length coding
+ /*
+ * instruction length coding
*
* aa - 16 bit aa != 11
* bbb11 - 32 bit bbb != 111
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 45/60] target/riscv: Fix target address to update badaddr
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (43 preceding siblings ...)
2023-06-14 1:20 ` [PULL 44/60] disas/riscv.c: Remove redundant parentheses Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext Alistair Francis
` (16 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it into badaddr
and restore cpu_pc to current pc if exception is triggered.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 21 ++++++++++-----------
target/riscv/insn_trans/trans_rvi.c.inc | 23 ++++++++++++++++-------
target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++--
3 files changed, 28 insertions(+), 20 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 29f1fb3995..6fbdb50c5d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -224,21 +224,18 @@ static void decode_save_opc(DisasContext *ctx)
ctx->insn_start = NULL;
}
-static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
+ target_ulong dest)
{
if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
}
- tcg_gen_movi_tl(cpu_pc, dest);
+ tcg_gen_movi_tl(target, dest);
}
-static void gen_set_pc(DisasContext *ctx, TCGv dest)
+static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
{
- if (get_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32s_tl(cpu_pc, dest);
- } else {
- tcg_gen_mov_tl(cpu_pc, dest);
- }
+ gen_pc_plus_diff(cpu_pc, ctx, dest);
}
static void generate_exception(DisasContext *ctx, int excp)
@@ -259,9 +256,9 @@ static void gen_exception_illegal(DisasContext *ctx)
}
}
-static void gen_exception_inst_addr_mis(DisasContext *ctx)
+static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target)
{
- tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+ tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr));
generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
}
@@ -553,7 +550,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
- gen_exception_inst_addr_mis(ctx);
+ TCGv target_pc = tcg_temp_new();
+ gen_pc_plus_diff(target_pc, ctx, next_pc);
+ gen_exception_inst_addr_mis(ctx, target_pc);
return;
}
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index d794247f40..009dc96dbd 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -51,25 +51,30 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
TCGLabel *misaligned = NULL;
+ TCGv target_pc = tcg_temp_new();
- tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+ tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
+ tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
+
+ if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32s_tl(target_pc, target_pc);
+ }
- gen_set_pc(ctx, cpu_pc);
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_andi_tl(t0, target_pc, 0x2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
}
gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
+ tcg_gen_mov_tl(cpu_pc, target_pc);
lookup_and_goto_ptr(ctx);
if (misaligned) {
gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
+ gen_exception_inst_addr_mis(ctx, target_pc);
}
ctx->base.is_jmp = DISAS_NORETURN;
@@ -153,6 +158,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
+ target_ulong next_pc;
if (get_xl(ctx) == MXL_RV128) {
TCGv src1h = get_gprh(ctx, a->rs1);
@@ -169,10 +175,13 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
+ next_pc = ctx->base.pc_next + a->imm;
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
- ((ctx->base.pc_next + a->imm) & 0x3)) {
+ (next_pc & 0x3)) {
/* misaligned */
- gen_exception_inst_addr_mis(ctx);
+ TCGv target_pc = tcg_temp_new();
+ gen_pc_plus_diff(target_pc, ctx, next_pc);
+ gen_exception_inst_addr_mis(ctx, target_pc);
} else {
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
}
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index a727169a4b..5732d782f7 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -202,8 +202,8 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
}
if (ret) {
- TCGv ret_addr = get_gpr(ctx, xRA, EXT_NONE);
- gen_set_pc(ctx, ret_addr);
+ TCGv ret_addr = get_gpr(ctx, xRA, EXT_SIGN);
+ tcg_gen_mov_tl(cpu_pc, ret_addr);
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (44 preceding siblings ...)
2023-06-14 1:20 ` [PULL 45/60] target/riscv: Fix target address to update badaddr Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements Alistair Francis
` (15 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Use cur_insn_len to store the length of the current instruction to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6fbdb50c5d..ea63d20eef 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -61,6 +61,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong cur_insn_len;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
@@ -1116,8 +1117,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
};
ctx->virt_inst_excp = false;
+ ctx->cur_insn_len = insn_len(opcode);
/* Check for compressed insn */
- if (insn_len(opcode) == 2) {
+ if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (45 preceding siblings ...)
2023-06-14 1:20 ` [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc Alistair Francis
` (14 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Reduce reliance on absolute value to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 8 +++++---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ea63d20eef..33c666d74e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -283,8 +283,10 @@ static void exit_tb(DisasContext *ctx)
tcg_gen_exit_tb(NULL, 0);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
{
+ target_ulong dest = ctx->base.pc_next + diff;
+
/*
* Under itrigger, instruction executes one by one like singlestep,
* direct block chain benefits will be small.
@@ -559,7 +561,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
}
gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
- gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
+ gen_goto_tb(ctx, 0, imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -1231,7 +1233,7 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
switch (ctx->base.is_jmp) {
case DISAS_TOO_MANY:
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
+ gen_goto_tb(ctx, 0, 0);
break;
case DISAS_NORETURN:
break;
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 009dc96dbd..321885f951 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -171,7 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
} else {
tcg_gen_brcond_tl(cond, src1, src2, l);
}
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_goto_tb(ctx, 1, ctx->cur_insn_len);
gen_set_label(l); /* branch taken */
@@ -183,7 +183,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_pc_plus_diff(target_pc, ctx, next_pc);
gen_exception_inst_addr_mis(ctx, target_pc);
} else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ gen_goto_tb(ctx, 0, a->imm);
}
ctx->base.is_jmp = DISAS_NORETURN;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (46 preceding siblings ...)
2023-06-14 1:20 ` [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff Alistair Francis
` (13 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Reduce reliance on absolute values(by passing pc difference) to
prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 10 +++++-----
target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/insn_trans/trans_rvzawrs.c.inc | 2 +-
target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
6 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 33c666d74e..eda022d10b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -234,14 +234,14 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
tcg_gen_movi_tl(target, dest);
}
-static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
+static void gen_update_pc(DisasContext *ctx, target_long diff)
{
- gen_pc_plus_diff(cpu_pc, ctx, dest);
+ gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
}
static void generate_exception(DisasContext *ctx, int excp)
{
- gen_set_pc_imm(ctx, ctx->base.pc_next);
+ gen_update_pc(ctx, 0);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -293,10 +293,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
*/
if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
tcg_gen_goto_tb(n);
- gen_set_pc_imm(ctx, dest);
+ gen_update_pc(ctx, diff);
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
- gen_set_pc_imm(ctx, dest);
+ gen_update_pc(ctx, diff);
lookup_and_goto_ptr(ctx);
}
}
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 528baa1652..dc14d7fc7a 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -108,7 +108,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
{
#ifndef CONFIG_USER_ONLY
decode_save_opc(ctx);
- gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ gen_update_pc(ctx, ctx->cur_insn_len);
gen_helper_wfi(cpu_env);
return true;
#else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 321885f951..4837e133cc 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -777,7 +777,7 @@ static bool trans_pause(DisasContext *ctx, arg_pause *a)
* PAUSE is a no-op in QEMU,
* end the TB and return to main loop
*/
- gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ gen_update_pc(ctx, ctx->cur_insn_len);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
@@ -801,7 +801,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
* FENCE_I is a no-op in QEMU,
* however we need to end the translation block
*/
- gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ gen_update_pc(ctx, ctx->cur_insn_len);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
@@ -812,7 +812,7 @@ static bool do_csr_post(DisasContext *ctx)
/* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
decode_save_opc(ctx);
/* We may have changed important cpu state -- exit to main loop. */
- gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ gen_update_pc(ctx, ctx->cur_insn_len);
exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c07eebc52..c2f7527f53 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -169,7 +169,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
gen_set_gpr(s, rd, dst);
mark_vs_dirty(s);
- gen_set_pc_imm(s, s->pc_succ_insn);
+ gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
return true;
@@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(s, rd, dst);
mark_vs_dirty(s);
- gen_set_pc_imm(s, s->pc_succ_insn);
+ gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index 8254e7dfe2..32efbff4d5 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -33,7 +33,7 @@ static bool trans_wrs(DisasContext *ctx)
/* Clear the load reservation (if any). */
tcg_gen_movi_tl(load_res, -1);
- gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ gen_update_pc(ctx, ctx->cur_insn_len);
tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index 3e13b1d74d..da093a4cec 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -999,7 +999,7 @@ static void gen_th_sync_local(DisasContext *ctx)
* Emulate out-of-order barriers with pipeline flush
* by exiting the translation block.
*/
- gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+ gen_update_pc(ctx, ctx->cur_insn_len);
tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (47 preceding siblings ...)
2023-06-14 1:20 ` [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 50/60] target/riscv: Enable PC-relative translation Alistair Francis
` (12 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Reduce reliance on absolute values by using true pc difference for
gen_pc_plus_diff() to prepare for PC-relative translation.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 13 ++++++-------
target/riscv/insn_trans/trans_rvi.c.inc | 6 ++----
target/riscv/insn_trans/trans_rvzce.c.inc | 2 +-
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index eda022d10b..7fb4cbe84c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -226,8 +226,10 @@ static void decode_save_opc(DisasContext *ctx)
}
static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
- target_ulong dest)
+ target_long diff)
{
+ target_ulong dest = ctx->base.pc_next + diff;
+
if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
}
@@ -236,7 +238,7 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
static void gen_update_pc(DisasContext *ctx, target_long diff)
{
- gen_pc_plus_diff(cpu_pc, ctx, ctx->base.pc_next + diff);
+ gen_pc_plus_diff(cpu_pc, ctx, diff);
}
static void generate_exception(DisasContext *ctx, int excp)
@@ -547,14 +549,11 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
- target_ulong next_pc;
-
/* check misaligned: */
- next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
- if ((next_pc & 0x3) != 0) {
+ if ((imm & 0x3) != 0) {
TCGv target_pc = tcg_temp_new();
- gen_pc_plus_diff(target_pc, ctx, next_pc);
+ gen_pc_plus_diff(target_pc, ctx, imm);
gen_exception_inst_addr_mis(ctx, target_pc);
return;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 4837e133cc..2d350cfbd7 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -158,7 +158,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
- target_ulong next_pc;
if (get_xl(ctx) == MXL_RV128) {
TCGv src1h = get_gprh(ctx, a->rs1);
@@ -175,12 +174,11 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
- next_pc = ctx->base.pc_next + a->imm;
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
- (next_pc & 0x3)) {
+ (a->imm & 0x3)) {
/* misaligned */
TCGv target_pc = tcg_temp_new();
- gen_pc_plus_diff(target_pc, ctx, next_pc);
+ gen_pc_plus_diff(target_pc, ctx, a->imm);
gen_exception_inst_addr_mis(ctx, target_pc);
} else {
gen_goto_tb(ctx, 0, a->imm);
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index 5732d782f7..450b79dcbc 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -297,7 +297,7 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
* Update pc to current for the non-unwinding exception
* that might come from cpu_ld*_code() in the helper.
*/
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+ gen_update_pc(ctx, 0);
gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index));
/* c.jt vs c.jalt depends on the index. */
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 50/60] target/riscv: Enable PC-relative translation
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (48 preceding siblings ...)
2023-06-14 1:20 ` [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext Alistair Francis
` (11 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 31 ++++++++++-----
target/riscv/translate.c | 47 +++++++++++++++++++----
target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++-
target/riscv/insn_trans/trans_rvzce.c.inc | 4 +-
4 files changed, 74 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 938c7bd87b..881bddf393 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -721,16 +721,18 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ if (!(tb_cflags(tb) & CF_PCREL)) {
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+ tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
- if (xl == MXL_RV32) {
- env->pc = (int32_t) tb->pc;
- } else {
- env->pc = tb->pc;
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t) tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
}
}
@@ -756,11 +758,18 @@ static void riscv_restore_state_to_opc(CPUState *cs,
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ target_ulong pc;
+
+ if (tb_cflags(tb) & CF_PCREL) {
+ pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+ } else {
+ pc = data[0];
+ }
if (xl == MXL_RV32) {
- env->pc = (int32_t)data[0];
+ env->pc = (int32_t)pc;
} else {
- env->pc = data[0];
+ env->pc = pc;
}
env->bins = data[1];
}
@@ -1343,6 +1352,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
#ifndef CONFIG_USER_ONLY
+ cs->tcg_cflags |= CF_PCREL;
+
if (cpu->cfg.ext_sstc) {
riscv_timer_init(cpu);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7fb4cbe84c..bd2da9b079 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -62,6 +62,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong cur_insn_len;
+ target_ulong pc_save;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
@@ -230,15 +231,24 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
{
target_ulong dest = ctx->base.pc_next + diff;
- if (get_xl(ctx) == MXL_RV32) {
- dest = (int32_t)dest;
+ assert(ctx->pc_save != -1);
+ if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+ tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save);
+ if (get_xl(ctx) == MXL_RV32) {
+ tcg_gen_ext32s_tl(target, target);
+ }
+ } else {
+ if (get_xl(ctx) == MXL_RV32) {
+ dest = (int32_t)dest;
+ }
+ tcg_gen_movi_tl(target, dest);
}
- tcg_gen_movi_tl(target, dest);
}
static void gen_update_pc(DisasContext *ctx, target_long diff)
{
gen_pc_plus_diff(cpu_pc, ctx, diff);
+ ctx->pc_save = ctx->base.pc_next + diff;
}
static void generate_exception(DisasContext *ctx, int excp)
@@ -294,8 +304,21 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
* direct block chain benefits will be small.
*/
if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
- tcg_gen_goto_tb(n);
- gen_update_pc(ctx, diff);
+ /*
+ * For pcrel, the pc must always be up-to-date on entry to
+ * the linked TB, so that it can use simple additions for all
+ * further adjustments. For !pcrel, the linked TB is compiled
+ * to know its full virtual address, so we can delay the
+ * update to pc to the unlinked path. A long chain of links
+ * can thus avoid many updates to the PC.
+ */
+ if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+ gen_update_pc(ctx, diff);
+ tcg_gen_goto_tb(n);
+ } else {
+ tcg_gen_goto_tb(n);
+ gen_update_pc(ctx, diff);
+ }
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
gen_update_pc(ctx, diff);
@@ -549,6 +572,8 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
+ TCGv succ_pc = dest_gpr(ctx, rd);
+
/* check misaligned: */
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((imm & 0x3) != 0) {
@@ -559,7 +584,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
}
}
- gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
+ gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+ gen_set_gpr(ctx, rd, succ_pc);
+
gen_goto_tb(ctx, 0, imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -1157,6 +1184,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags;
+ ctx->pc_save = ctx->base.pc_first;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
@@ -1192,8 +1220,13 @@ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ target_ulong pc_next = ctx->base.pc_next;
+
+ if (tb_cflags(dcbase->tb) & CF_PCREL) {
+ pc_next &= ~TARGET_PAGE_MASK;
+ }
- tcg_gen_insn_start(ctx->base.pc_next, 0);
+ tcg_gen_insn_start(pc_next, 0);
ctx->insn_start = tcg_last_op();
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 2d350cfbd7..297142208e 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -38,7 +38,9 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
- gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
+ TCGv target_pc = dest_gpr(ctx, a->rd);
+ gen_pc_plus_diff(target_pc, ctx, a->imm);
+ gen_set_gpr(ctx, a->rd, target_pc);
return true;
}
@@ -52,6 +54,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
TCGLabel *misaligned = NULL;
TCGv target_pc = tcg_temp_new();
+ TCGv succ_pc = dest_gpr(ctx, a->rd);
tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
@@ -68,7 +71,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
}
- gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
+ gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+ gen_set_gpr(ctx, a->rd, succ_pc);
+
tcg_gen_mov_tl(cpu_pc, target_pc);
lookup_and_goto_ptr(ctx);
@@ -158,6 +163,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
+ target_ulong orig_pc_save = ctx->pc_save;
if (get_xl(ctx) == MXL_RV128) {
TCGv src1h = get_gprh(ctx, a->rs1);
@@ -171,6 +177,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
tcg_gen_brcond_tl(cond, src1, src2, l);
}
gen_goto_tb(ctx, 1, ctx->cur_insn_len);
+ ctx->pc_save = orig_pc_save;
gen_set_label(l); /* branch taken */
@@ -183,6 +190,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
} else {
gen_goto_tb(ctx, 0, a->imm);
}
+ ctx->pc_save = -1;
ctx->base.is_jmp = DISAS_NORETURN;
return true;
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index 450b79dcbc..8d8a64f493 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -302,7 +302,9 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
/* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) {
- gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
+ TCGv succ_pc = dest_gpr(ctx, xRA);
+ gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
+ gen_set_gpr(ctx, xRA, succ_pc);
}
tcg_gen_lookup_and_goto_ptr();
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (49 preceding siblings ...)
2023-06-14 1:20 ` [PULL 50/60] target/riscv: Enable PC-relative translation Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" Alistair Francis
` (10 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, Richard Henderson,
Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bd2da9b079..8a33da811e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -59,8 +59,6 @@ typedef enum {
typedef struct DisasContext {
DisasContextBase base;
- /* pc_succ_insn points to the instruction following base.pc_next */
- target_ulong pc_succ_insn;
target_ulong cur_insn_len;
target_ulong pc_save;
target_ulong priv_ver;
@@ -1149,7 +1147,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
/* Check for compressed insn */
if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
- ctx->pc_succ_insn = ctx->base.pc_next + 2;
/*
* The Zca extension is added as way to refer to instructions in the C
* extension that do not include the floating-point loads and stores
@@ -1164,7 +1161,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
- ctx->pc_succ_insn = ctx->base.pc_next + 4;
for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
if (decoders[i].guard_func(ctx) &&
@@ -1185,7 +1181,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_save = ctx->base.pc_first;
- ctx->pc_succ_insn = ctx->base.pc_first;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
@@ -1238,7 +1233,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
- ctx->base.pc_next = ctx->pc_succ_insn;
+ ctx->base.pc_next += ctx->cur_insn_len;
/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (50 preceding siblings ...)
2023-06-14 1:20 ` [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 53/60] riscv/virt: Support using pflash via -blockdev option Alistair Francis
` (9 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Sunil V L, Heinrich Schuchardt, Andrea Bolognani,
Alistair Francis
From: Sunil V L <sunilvl@ventanamicro.com>
Currently, virt machine supports two pflash instances each with
32MB size. However, the first pflash is always assumed to
contain M-mode firmware and reset vector is set to this if
enabled. Hence, for S-mode payloads like EDK2, only one pflash
instance is available for use. This means both code and NV variables
of EDK2 will need to use the same pflash.
The OS distros keep the EDK2 FW code as readonly. When non-volatile
variables also need to share the same pflash, it is not possible
to keep it as readonly since variables need write access.
To resolve this issue, the code and NV variables need to be separated.
But in that case we need an extra flash. Hence, modify the convention
for non-KVM guests such that, pflash0 will contain the M-mode FW
only when "-bios none" option is used. Otherwise, pflash0 will contain
the S-mode payload FW. This enables both pflash instances available
for EDK2 use.
When KVM is enabled, pflash0 is always assumed to contain the
S-mode payload firmware only.
Example usage:
1) pflash0 containing M-mode FW
qemu-system-riscv64 -bios none -pflash <mmode_fw> -machine virt
or
qemu-system-riscv64 -bios none \
-drive file=<mmode_fw>,if=pflash,format=raw,unit=0 -machine virt
2) pflash0 containing S-mode payload like EDK2
qemu-system-riscv64 -pflash <smode_fw_code> -pflash <smode_vars> -machine virt
or
qemu-system-riscv64 -bios <opensbi_fw> \
-pflash <smode_fw_code> \
-pflash <smode_vars> \
-machine virt
or
qemu-system-riscv64 -bios <opensbi_fw> \
-drive file=<smode_fw_code>,if=pflash,format=raw,unit=0,readonly=on \
-drive file=<smode_fw_vars>,if=pflash,format=raw,unit=1 \
-machine virt
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-2-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 53 ++++++++++++++++++++-----------------------------
1 file changed, 21 insertions(+), 32 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 245c7b97b2..17fdcef223 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1245,7 +1245,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
target_ulong firmware_end_addr, kernel_start_addr;
const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
uint32_t fdt_load_addr;
- uint64_t kernel_entry;
+ uint64_t kernel_entry = 0;
/*
* Only direct boot kernel is currently supported for KVM VM,
@@ -1266,42 +1266,31 @@ static void virt_machine_done(Notifier *notifier, void *data)
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
start_addr, NULL);
- if (drive_get(IF_PFLASH, 0, 1)) {
- /*
- * S-mode FW like EDK2 will be kept in second plash (unit 1).
- * When both kernel, initrd and pflash options are provided in the
- * command line, the kernel and initrd will be copied to the fw_cfg
- * table and opensbi will jump to the flash address which is the
- * entry point of S-mode FW. It is the job of the S-mode FW to load
- * the kernel and initrd using fw_cfg table.
- *
- * If only pflash is given but not -kernel, then it is the job of
- * of the S-mode firmware to locate and load the kernel.
- * In either case, the next_addr for opensbi will be the flash address.
- */
- riscv_setup_firmware_boot(machine);
- kernel_entry = virt_memmap[VIRT_FLASH].base +
- virt_memmap[VIRT_FLASH].size / 2;
- } else if (machine->kernel_filename) {
+ if (drive_get(IF_PFLASH, 0, 0)) {
+ if (machine->firmware && !strcmp(machine->firmware, "none") &&
+ !kvm_enabled()) {
+ /*
+ * Pflash was supplied but bios is none and not KVM guest,
+ * let's overwrite the address we jump to after reset to
+ * the base of the flash.
+ */
+ start_addr = virt_memmap[VIRT_FLASH].base;
+ } else {
+ /*
+ * Pflash was supplied but either KVM guest or bios is not none.
+ * In this case, base of the flash would contain S-mode payload.
+ */
+ riscv_setup_firmware_boot(machine);
+ kernel_entry = virt_memmap[VIRT_FLASH].base;
+ }
+ }
+
+ if (machine->kernel_filename && !kernel_entry) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, &s->soc[0],
kernel_start_addr, true, NULL);
- } else {
- /*
- * If dynamic firmware is used, it doesn't know where is the next mode
- * if kernel argument is not set.
- */
- kernel_entry = 0;
- }
-
- if (drive_get(IF_PFLASH, 0, 0)) {
- /*
- * Pflash was supplied, let's overwrite the address we jump to after
- * reset to the base of the flash.
- */
- start_addr = virt_memmap[VIRT_FLASH].base;
}
fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 53/60] riscv/virt: Support using pflash via -blockdev option
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (51 preceding siblings ...)
2023-06-14 1:20 ` [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 54/60] docs/system: riscv: Add pflash usage details Alistair Francis
` (8 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Sunil V L, Andrea Bolognani,
Philippe Mathieu-Daudé,
Alistair Francis
From: Sunil V L <sunilvl@ventanamicro.com>
Currently, pflash devices can be configured only via -pflash
or -drive options. This is the legacy way and the
better way is to use -blockdev as in other architectures.
libvirt also has moved to use -blockdev method.
To support -blockdev option, pflash devices need to be
created in instance_init itself. So, update the code to
move the virt_flash_create() to instance_init. Also, use
standard interfaces to detect whether pflash0 is
configured or not.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reported-by: Andrea Bolognani <abologna@redhat.com>
Tested-by: Andrea Bolognani <abologna@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-3-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 17fdcef223..95708d890e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1246,6 +1246,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
uint32_t fdt_load_addr;
uint64_t kernel_entry = 0;
+ BlockBackend *pflash_blk0;
/*
* Only direct boot kernel is currently supported for KVM VM,
@@ -1266,7 +1267,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
start_addr, NULL);
- if (drive_get(IF_PFLASH, 0, 0)) {
+ pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);
+ if (pflash_blk0) {
if (machine->firmware && !strcmp(machine->firmware, "none") &&
!kvm_enabled()) {
/*
@@ -1499,8 +1501,6 @@ static void virt_machine_init(MachineState *machine)
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
qdev_get_gpio_in(mmio_irqchip, RTC_IRQ));
- virt_flash_create(s);
-
for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
/* Map legacy -drive if=pflash to machine properties */
pflash_cfi01_legacy_drive(s->flash[i],
@@ -1527,6 +1527,8 @@ static void virt_machine_instance_init(Object *obj)
{
RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+ virt_flash_create(s);
+
s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
s->acpi = ON_OFF_AUTO_AUTO;
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 54/60] docs/system: riscv: Add pflash usage details
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (52 preceding siblings ...)
2023-06-14 1:20 ` [PULL 53/60] riscv/virt: Support using pflash via -blockdev option Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 55/60] util/log: Add vector registers to log Alistair Francis
` (7 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Sunil V L, Philippe Mathieu-Daudé, Alistair Francis
From: Sunil V L <sunilvl@ventanamicro.com>
pflash devices can be used in virt machine for different
purposes like for ROM code or S-mode FW payload. Add a
section in the documentation on how to use pflash devices
for different purposes.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 4b16e41d7f..b33f45e5b3 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -53,6 +53,37 @@ with the default OpenSBI firmware image as the -bios. It also supports
the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
firmware and U-Boot proper (S-mode), using the standard -bios functionality.
+Using flash devices
+-------------------
+
+By default, the first flash device (pflash0) is expected to contain
+S-mode firmware code. It can be configured as read-only, with the
+second flash device (pflash1) available to store configuration data.
+
+For example, booting edk2 looks like
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 \
+ -blockdev node-name=pflash0,driver=file,read-only=on,filename=<edk2_code> \
+ -blockdev node-name=pflash1,driver=file,filename=<edk2_vars> \
+ -M virt,pflash0=pflash0,pflash1=pflash1 \
+ ... other args ....
+
+For TCG guests only, it is also possible to boot M-mode firmware from
+the first flash device (pflash0) by additionally passing ``-bios
+none``, as in
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 \
+ -bios none \
+ -blockdev node-name=pflash0,driver=file,read-only=on,filename=<m_mode_code> \
+ -M virt,pflash0=pflash0 \
+ ... other args ....
+
+Firmware images used for pflash must be exactly 32 MiB in size.
+
Machine-specific options
------------------------
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 55/60] util/log: Add vector registers to log
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (53 preceding siblings ...)
2023-06-14 1:20 ` [PULL 54/60] docs/system: riscv: Add pflash usage details Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask Alistair Francis
` (6 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Ivan Klokov, Alistair Francis
From: Ivan Klokov <ivan.klokov@syntacore.com>
Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230410124451.15929-2-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/core/cpu.h | 2 ++
include/qemu/log.h | 1 +
accel/tcg/cpu-exec.c | 3 +++
util/log.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 383456d1b3..d84fbccaab 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -544,11 +544,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
* @CPU_DUMP_CODE:
* @CPU_DUMP_FPU: dump FPU register state, not just integer
* @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
+ * @CPU_DUMP_VPU: dump VPU registers
*/
enum CPUDumpFlags {
CPU_DUMP_CODE = 0x00010000,
CPU_DUMP_FPU = 0x00020000,
CPU_DUMP_CCOP = 0x00040000,
+ CPU_DUMP_VPU = 0x00080000,
};
/**
diff --git a/include/qemu/log.h b/include/qemu/log.h
index c5643d8dd5..df59bfabcd 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -35,6 +35,7 @@ bool qemu_log_separate(void);
/* LOG_STRACE is used for user-mode strace logging. */
#define LOG_STRACE (1 << 19)
#define LOG_PER_THREAD (1 << 20)
+#define CPU_LOG_TB_VPU (1 << 21)
/* Lock/unlock output. */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 42086525d7..ebc1db03d7 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -313,6 +313,9 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu,
#if defined(TARGET_I386)
flags |= CPU_DUMP_CCOP;
#endif
+ if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) {
+ flags |= CPU_DUMP_VPU;
+ }
cpu_dump_state(cpu, logfile, flags);
qemu_log_unlock(logfile);
}
diff --git a/util/log.c b/util/log.c
index 53b4f6c58e..def88a9402 100644
--- a/util/log.c
+++ b/util/log.c
@@ -495,6 +495,8 @@ const QEMULogItem qemu_log_items[] = {
"log every user-mode syscall, its input, and its result" },
{ LOG_PER_THREAD, "tid",
"open a separate log file per thread; filename must contain '%d'" },
+ { CPU_LOG_TB_VPU, "vpu",
+ "include VPU registers in the 'cpu' logging" },
{ 0, NULL, NULL },
};
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (54 preceding siblings ...)
2023-06-14 1:20 ` [PULL 55/60] util/log: Add vector registers to log Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE Alistair Francis
` (5 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Weiwei Li, Junqiang Wang, LIU Zhiwei, Alistair Francis
From: Weiwei Li <liweiwei@iscas.ac.cn>
We initialize cur_pmmask as -1(UINT32_MAX/UINT64_MAX) and regard it
as if pointer mask is disabled in current implementation. However,
the addresses for vector load/store will be adjusted to zero in this
case and -1(UINT32_MAX/UINT64_MAX) is valid value for pmmask when
pointer mask is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230610094651.43786-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 523311b184..90cef9856d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -134,7 +134,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);
flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
- if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
+ if (env->cur_pmmask != 0) {
flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
}
if (env->cur_pmbase != 0) {
@@ -146,7 +146,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
void riscv_cpu_update_mask(CPURISCVState *env)
{
- target_ulong mask = -1, base = 0;
+ target_ulong mask = 0, base = 0;
/*
* TODO: Current RVJ spec does not specify
* how the extension interacts with XLEN.
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (55 preceding siblings ...)
2023-06-14 1:20 ` [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements Alistair Francis
` (4 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Xiao Wang, Daniel Henrique Barboza, LIU Zhiwei,
Alistair Francis
From: Xiao Wang <xiao.w.wang@intel.com>
There's no code using MTYPE, which was a concept used in older vector
implementation.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230608053517.4102648-1-xiao.w.wang@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7505f9470a..e8af64e626 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -388,7 +388,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
/*
* masked unit-stride load and store operation will be a special case of
- * stride, stride = NF * sizeof (MTYPE)
+ * stride, stride = NF * sizeof (ETYPE)
*/
#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \
@@ -660,10 +660,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-/* Unsigned min/max */
-#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
-#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
-
/*
* load and store whole register instructions
*/
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (56 preceding siblings ...)
2023-06-14 1:20 ` [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP Alistair Francis
` (3 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Xiao Wang, Daniel Henrique Barboza, Weiwei Li,
Alistair Francis
From: Xiao Wang <xiao.w.wang@intel.com>
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added an extra check for LMUL fragmentation,
intended for setting the "rest tail elements" in the last register for a
segment load insn.
Actually, the max_elements derived in vext_ld*() won't be a fraction of
vector register size, since the lmul encoded in desc is emul, which has
already been adjusted to 1 for LMUL fragmentation case by vext_get_emul()
in trans_rvv.c.inc, for ld_stride(), ld_us(), ld_index() and ldff().
Besides, vext_get_emul() has also taken EEW/SEW into consideration, so no
need to call vext_get_total_elems() which would base on the emul to derive
another emul, the second emul would be incorrect when esz differs from sew.
Thus this patch removes the check for extra tail elements.
Fixes: 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions")
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230607091646.4049428-1-xiao.w.wang@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 22 ++++++----------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e8af64e626..1e06e7447c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -264,11 +264,10 @@ GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq)
-static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
- void *vd, uint32_t desc, uint32_t nf,
+static void vext_set_tail_elems_1s(target_ulong vl, void *vd,
+ uint32_t desc, uint32_t nf,
uint32_t esz, uint32_t max_elems)
{
- uint32_t total_elems, vlenb, registers_used;
uint32_t vta = vext_vta(desc);
int k;
@@ -276,19 +275,10 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl,
return;
}
- total_elems = vext_get_total_elems(env, desc, esz);
- vlenb = riscv_cpu_cfg(env)->vlen >> 3;
-
for (k = 0; k < nf; ++k) {
vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz,
(k * max_elems + max_elems) * esz);
}
-
- if (nf * max_elems % total_elems != 0) {
- registers_used = ((nf * max_elems) * esz + (vlenb - 1)) / vlenb;
- vext_set_elems_1s(vd, vta, (nf * max_elems) * esz,
- registers_used * vlenb);
- }
}
/*
@@ -324,7 +314,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
}
env->vstart = 0;
- vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
+ vext_set_tail_elems_1s(env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
@@ -383,7 +373,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
}
env->vstart = 0;
- vext_set_tail_elems_1s(env, evl, vd, desc, nf, esz, max_elems);
+ vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems);
}
/*
@@ -504,7 +494,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
}
env->vstart = 0;
- vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
+ vext_set_tail_elems_1s(env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
@@ -634,7 +624,7 @@ ProbeSuccess:
}
env->vstart = 0;
- vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems);
+ vext_set_tail_elems_1s(env->vl, vd, desc, nf, esz, max_elems);
}
#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (57 preceding siblings ...)
2023-06-14 1:20 ` [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 1:20 ` [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Alistair Francis
` (2 subsequent siblings)
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Himanshu Chauhan, Daniel Henrique Barboza, Weiwei Li,
Alistair Francis
From: Himanshu Chauhan <hchauhan@ventanamicro.com>
On an address match, skip checking for default permissions and return error
based on access defined in PMP configuration.
v3 Changes:
o Removed explicit return of boolean value from comparision
of priv/allowed_priv
v2 Changes:
o Removed goto to return in place when address matches
o Call pmp_hart_has_privs_default at the end of the loop
Fixes: 90b1fafce06 ("target/riscv: Smepmp: Skip applying default rules when address matches")
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230605164548.715336-1-hchauhan@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 418738afd8..9d8db493e6 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -291,7 +291,6 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
pmp_priv_t *allowed_privs, target_ulong mode)
{
int i = 0;
- bool ret = false;
int pmp_size = 0;
target_ulong s = 0;
target_ulong e = 0;
@@ -435,17 +434,12 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
* defined with PMP must be used. We shouldn't fallback on
* finding default privileges.
*/
- ret = true;
- break;
+ return (privs & *allowed_privs) == privs;
}
}
/* No rule matched */
- if (!ret) {
- ret = pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
- }
-
- return ret;
+ return pmp_hart_has_privs_default(env, privs, allowed_privs, mode);
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (58 preceding siblings ...)
2023-06-14 1:20 ` [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP Alistair Francis
@ 2023-06-14 1:20 ` Alistair Francis
2023-06-14 4:39 ` [PULL 00/60] riscv-to-apply queue Richard Henderson
2023-06-14 12:17 ` Michael Tokarev
61 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-14 1:20 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Tommy Wu, Frank Chang, Alistair Francis, Anup Patel
From: Tommy Wu <tommy.wu@sifive.com>
According to the `The RISC-V Advanced Interrupt Architecture`
document, if register `mmsiaddrcfgh` of the domain has bit L set
to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20230609055936.3925438-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aplic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index afc5b54dbb..4bdc6a5d1a 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -688,13 +688,13 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
* domains).
*/
if (aplic->num_children &&
- !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
aplic->smsicfgaddr = value;
}
} else if (aplic->mmode && aplic->msimode &&
(addr == APLIC_SMSICFGADDRH)) {
if (aplic->num_children &&
- !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
}
} else if ((APLIC_SETIP_BASE <= addr) &&
--
2.40.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PULL 00/60] riscv-to-apply queue
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (59 preceding siblings ...)
2023-06-14 1:20 ` [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Alistair Francis
@ 2023-06-14 4:39 ` Richard Henderson
2023-06-14 12:17 ` Michael Tokarev
61 siblings, 0 replies; 64+ messages in thread
From: Richard Henderson @ 2023-06-14 4:39 UTC (permalink / raw)
To: Alistair Francis, qemu-devel; +Cc: Alistair Francis
On 6/14/23 03:19, Alistair Francis wrote:
> The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
>
> Merge tag 'pull-ppc-20230610' ofhttps://gitlab.com/danielhb/qemu into staging (2023-06-10 07:25:00 -0700)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
>
> for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
>
> hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. (2023-06-14 10:04:30 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for 8.1
>
> * Skip Vector set tail when vta is zero
> * Move zc* out of the experimental properties
> * Mask the implicitly enabled extensions in isa_string based on priv version
> * Rework CPU extension validation and validate MISA changes
> * Fixup PMP TLB cacheing errors
> * Writing to pmpaddr and MML/MMWP correctly triggers TLB flushes
> * Fixup PMP bypass checks
> * Deny access if access is partially inside a PMP entry
> * Correct OpenTitanState parent type/size
> * Fix QEMU crash when NUMA nodes exceed available CPUs
> * Fix pointer mask transformation for vector address
> * Updates and improvements for Smstateen
> * Support disas for Zcm* extensions
> * Support disas for Z*inx extensions
> * Remove unused decomp_rv32/64 value for vector instructions
> * Enable PC-relative translation
> * Assume M-mode FW in pflash0 only when "-bios none"
> * Support using pflash via -blockdev option
> * Add vector registers to log
> * Clean up reference of Vector MTYPE
> * Remove the check for extra Vector tail elements
> * Smepmp: Return error when access permission not allowed in PMP
> * Fixes for smsiaddrcfg and smsiaddrcfgh in AIA
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PULL 00/60] riscv-to-apply queue
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
` (60 preceding siblings ...)
2023-06-14 4:39 ` [PULL 00/60] riscv-to-apply queue Richard Henderson
@ 2023-06-14 12:17 ` Michael Tokarev
2023-06-15 4:03 ` Alistair Francis
61 siblings, 1 reply; 64+ messages in thread
From: Michael Tokarev @ 2023-06-14 12:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel; +Cc: Alistair Francis
14.06.2023 04:19, Alistair Francis wrote:
> The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
>
> Merge tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu into staging (2023-06-10 07:25:00 -0700)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
>
> for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
>
> hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. (2023-06-14 10:04:30 +1000)
Is anything there worth to apply to -stable?
I picked this one:
hw/riscv: qemu crash when NUMA nodes exceed available CPUs
Anything else?
Thanks!
/mjt
> Daniel Henrique Barboza (10):
> target/riscv/vector_helper.c: skip set tail when vta is zero
> target/riscv/cpu.c: add riscv_cpu_validate_v()
> target/riscv/cpu.c: remove set_vext_version()
> target/riscv/cpu.c: remove set_priv_version()
> target/riscv: add PRIV_VERSION_LATEST
> target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
> target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
> target/riscv/cpu.c: validate extensions before riscv_timer_init()
> target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
> target/riscv: rework write_misa()
>
> Himanshu Chauhan (1):
> target/riscv: Smepmp: Return error when access permission not allowed in PMP
>
> Ivan Klokov (1):
> util/log: Add vector registers to log
>
> Mayuresh Chitale (3):
> target/riscv: smstateen check for fcsr
> target/riscv: Reuse tb->flags.FS
> target/riscv: smstateen knobs
>
> Philippe Mathieu-Daudé (5):
> hw/riscv/opentitan: Rename machine_[class]_init() functions
> hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
> hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
> hw/riscv/opentitan: Explicit machine type definition
> hw/riscv/opentitan: Correct OpenTitanState parent type/size
>
> Sunil V L (3):
> hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
> riscv/virt: Support using pflash via -blockdev option
> docs/system: riscv: Add pflash usage details
>
> Tommy Wu (1):
> hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
>
> Weiwei Li (33):
> target/riscv: Move zc* out of the experimental properties
> target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
> target/riscv: Update check for Zca/Zcf/Zcd
> target/riscv: Update pmp_get_tlb_size()
> target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
> target/riscv: Make the short cut really work in pmp_hart_has_privs
> target/riscv: Change the return type of pmp_hart_has_privs() to bool
> target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
> target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
> target/riscv: Flush TLB when MMWP or MML bits are changed
> target/riscv: Update the next rule addr in pmpaddr_csr_write()
> target/riscv: Flush TLB when pmpaddr is updated
> target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
> target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
> target/riscv: Deny access if access is partially inside the PMP entry
> target/riscv: Fix pointer mask transformation for vector address
> target/riscv: Update cur_pmmask/base when xl changes
> disas: Change type of disassemble_info.target_info to pointer
> target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
> target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
> disas/riscv.c: Support disas for Zcm* extensions
> disas/riscv.c: Support disas for Z*inx extensions
> disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
> disas/riscv.c: Fix lines with over 80 characters
> disas/riscv.c: Remove redundant parentheses
> target/riscv: Fix target address to update badaddr
> target/riscv: Introduce cur_insn_len into DisasContext
> target/riscv: Change gen_goto_tb to work on displacements
> target/riscv: Change gen_set_pc_imm to gen_update_pc
> target/riscv: Use true diff for gen_pc_plus_diff
> target/riscv: Enable PC-relative translation
> target/riscv: Remove pc_succ_insn from DisasContext
> target/riscv: Fix initialized value for cur_pmmask
>
> Xiao Wang (2):
> target/riscv/vector_helper.c: clean up reference of MTYPE
> target/riscv/vector_helper.c: Remove the check for extra tail elements
>
> Yin Wang (1):
> hw/riscv: qemu crash when NUMA nodes exceed available CPUs
>
> docs/system/riscv/virt.rst | 31 +
> include/disas/dis-asm.h | 2 +-
> include/hw/core/cpu.h | 2 +
> include/hw/riscv/opentitan.h | 6 +-
> include/qemu/log.h | 1 +
> target/riscv/cpu.h | 117 +--
> target/riscv/cpu_cfg.h | 136 +++
> target/riscv/pmp.h | 11 +-
> accel/tcg/cpu-exec.c | 3 +
> disas/riscv.c | 1194 +++++++++++++-----------
> hw/intc/riscv_aplic.c | 4 +-
> hw/riscv/numa.c | 6 +
> hw/riscv/opentitan.c | 38 +-
> hw/riscv/virt.c | 59 +-
> target/riscv/cpu.c | 384 +++++---
> target/riscv/cpu_helper.c | 37 +-
> target/riscv/csr.c | 75 +-
> target/riscv/pmp.c | 205 ++--
> target/riscv/translate.c | 99 +-
> target/riscv/vector_helper.c | 33 +-
> util/log.c | 2 +
> target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
> target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
> target/riscv/insn_trans/trans_rvf.c.inc | 21 +-
> target/riscv/insn_trans/trans_rvi.c.inc | 46 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 4 +-
> target/riscv/insn_trans/trans_rvzawrs.c.inc | 2 +-
> target/riscv/insn_trans/trans_rvzce.c.inc | 10 +-
> target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
> 29 files changed, 1442 insertions(+), 1102 deletions(-)
> create mode 100644 target/riscv/cpu_cfg.h
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PULL 00/60] riscv-to-apply queue
2023-06-14 12:17 ` Michael Tokarev
@ 2023-06-15 4:03 ` Alistair Francis
0 siblings, 0 replies; 64+ messages in thread
From: Alistair Francis @ 2023-06-15 4:03 UTC (permalink / raw)
To: Michael Tokarev; +Cc: qemu-devel, Alistair Francis
On Wed, Jun 14, 2023 at 10:17 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 14.06.2023 04:19, Alistair Francis wrote:
> > The following changes since commit fdd0df5340a8ebc8de88078387ebc85c5af7b40f:
> >
> > Merge tag 'pull-ppc-20230610' of https://gitlab.com/danielhb/qemu into staging (2023-06-10 07:25:00 -0700)
> >
> > are available in the Git repository at:
> >
> > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
> >
> > for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
> >
> > hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only. (2023-06-14 10:04:30 +1000)
>
> Is anything there worth to apply to -stable?
>
> I picked this one:
> hw/riscv: qemu crash when NUMA nodes exceed available CPUs
Thanks for that!
>
> Anything else?
I don't think there is anything else, the other fixes are mostly for
experimental features, so I don't think we need to backport them.
Alistair
>
> Thanks!
>
> /mjt
>
> > Daniel Henrique Barboza (10):
> > target/riscv/vector_helper.c: skip set tail when vta is zero
> > target/riscv/cpu.c: add riscv_cpu_validate_v()
> > target/riscv/cpu.c: remove set_vext_version()
> > target/riscv/cpu.c: remove set_priv_version()
> > target/riscv: add PRIV_VERSION_LATEST
> > target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
> > target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
> > target/riscv/cpu.c: validate extensions before riscv_timer_init()
> > target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
> > target/riscv: rework write_misa()
> >
> > Himanshu Chauhan (1):
> > target/riscv: Smepmp: Return error when access permission not allowed in PMP
> >
> > Ivan Klokov (1):
> > util/log: Add vector registers to log
> >
> > Mayuresh Chitale (3):
> > target/riscv: smstateen check for fcsr
> > target/riscv: Reuse tb->flags.FS
> > target/riscv: smstateen knobs
> >
> > Philippe Mathieu-Daudé (5):
> > hw/riscv/opentitan: Rename machine_[class]_init() functions
> > hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro
> > hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition
> > hw/riscv/opentitan: Explicit machine type definition
> > hw/riscv/opentitan: Correct OpenTitanState parent type/size
> >
> > Sunil V L (3):
> > hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
> > riscv/virt: Support using pflash via -blockdev option
> > docs/system: riscv: Add pflash usage details
> >
> > Tommy Wu (1):
> > hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
> >
> > Weiwei Li (33):
> > target/riscv: Move zc* out of the experimental properties
> > target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version
> > target/riscv: Update check for Zca/Zcf/Zcd
> > target/riscv: Update pmp_get_tlb_size()
> > target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp
> > target/riscv: Make the short cut really work in pmp_hart_has_privs
> > target/riscv: Change the return type of pmp_hart_has_privs() to bool
> > target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled
> > target/riscv: Remove unused paramters in pmp_hart_has_privs_default()
> > target/riscv: Flush TLB when MMWP or MML bits are changed
> > target/riscv: Update the next rule addr in pmpaddr_csr_write()
> > target/riscv: Flush TLB when pmpaddr is updated
> > target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
> > target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
> > target/riscv: Deny access if access is partially inside the PMP entry
> > target/riscv: Fix pointer mask transformation for vector address
> > target/riscv: Update cur_pmmask/base when xl changes
> > disas: Change type of disassemble_info.target_info to pointer
> > target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h
> > target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
> > disas/riscv.c: Support disas for Zcm* extensions
> > disas/riscv.c: Support disas for Z*inx extensions
> > disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
> > disas/riscv.c: Fix lines with over 80 characters
> > disas/riscv.c: Remove redundant parentheses
> > target/riscv: Fix target address to update badaddr
> > target/riscv: Introduce cur_insn_len into DisasContext
> > target/riscv: Change gen_goto_tb to work on displacements
> > target/riscv: Change gen_set_pc_imm to gen_update_pc
> > target/riscv: Use true diff for gen_pc_plus_diff
> > target/riscv: Enable PC-relative translation
> > target/riscv: Remove pc_succ_insn from DisasContext
> > target/riscv: Fix initialized value for cur_pmmask
> >
> > Xiao Wang (2):
> > target/riscv/vector_helper.c: clean up reference of MTYPE
> > target/riscv/vector_helper.c: Remove the check for extra tail elements
> >
> > Yin Wang (1):
> > hw/riscv: qemu crash when NUMA nodes exceed available CPUs
> >
> > docs/system/riscv/virt.rst | 31 +
> > include/disas/dis-asm.h | 2 +-
> > include/hw/core/cpu.h | 2 +
> > include/hw/riscv/opentitan.h | 6 +-
> > include/qemu/log.h | 1 +
> > target/riscv/cpu.h | 117 +--
> > target/riscv/cpu_cfg.h | 136 +++
> > target/riscv/pmp.h | 11 +-
> > accel/tcg/cpu-exec.c | 3 +
> > disas/riscv.c | 1194 +++++++++++++-----------
> > hw/intc/riscv_aplic.c | 4 +-
> > hw/riscv/numa.c | 6 +
> > hw/riscv/opentitan.c | 38 +-
> > hw/riscv/virt.c | 59 +-
> > target/riscv/cpu.c | 384 +++++---
> > target/riscv/cpu_helper.c | 37 +-
> > target/riscv/csr.c | 75 +-
> > target/riscv/pmp.c | 205 ++--
> > target/riscv/translate.c | 99 +-
> > target/riscv/vector_helper.c | 33 +-
> > util/log.c | 2 +
> > target/riscv/insn_trans/trans_privileged.c.inc | 2 +-
> > target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
> > target/riscv/insn_trans/trans_rvf.c.inc | 21 +-
> > target/riscv/insn_trans/trans_rvi.c.inc | 46 +-
> > target/riscv/insn_trans/trans_rvv.c.inc | 4 +-
> > target/riscv/insn_trans/trans_rvzawrs.c.inc | 2 +-
> > target/riscv/insn_trans/trans_rvzce.c.inc | 10 +-
> > target/riscv/insn_trans/trans_xthead.c.inc | 2 +-
> > 29 files changed, 1442 insertions(+), 1102 deletions(-)
> > create mode 100644 target/riscv/cpu_cfg.h
> >
>
^ permalink raw reply [flat|nested] 64+ messages in thread
end of thread, other threads:[~2023-06-15 4:05 UTC | newest]
Thread overview: 64+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
2023-06-14 1:19 ` [PULL 02/60] target/riscv: Move zc* out of the experimental properties Alistair Francis
2023-06-14 1:19 ` [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() Alistair Francis
2023-06-14 1:19 ` [PULL 04/60] target/riscv/cpu.c: remove set_vext_version() Alistair Francis
2023-06-14 1:19 ` [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Alistair Francis
2023-06-14 1:19 ` [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST Alistair Francis
2023-06-14 1:19 ` [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Alistair Francis
2023-06-14 1:19 ` [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd Alistair Francis
2023-06-14 1:19 ` [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Alistair Francis
2023-06-14 1:19 ` [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Alistair Francis
2023-06-14 1:19 ` [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() Alistair Francis
2023-06-14 1:19 ` [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Alistair Francis
2023-06-14 1:19 ` [PULL 13/60] target/riscv: rework write_misa() Alistair Francis
2023-06-14 1:19 ` [PULL 14/60] target/riscv: Update pmp_get_tlb_size() Alistair Francis
2023-06-14 1:19 ` [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Alistair Francis
2023-06-14 1:19 ` [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs Alistair Francis
2023-06-14 1:19 ` [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool Alistair Francis
2023-06-14 1:19 ` [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Alistair Francis
2023-06-14 1:19 ` [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Alistair Francis
2023-06-14 1:19 ` [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed Alistair Francis
2023-06-14 1:19 ` [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() Alistair Francis
2023-06-14 1:19 ` [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated Alistair Francis
2023-06-14 1:19 ` [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Alistair Francis
2023-06-14 1:19 ` [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Alistair Francis
2023-06-14 1:19 ` [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry Alistair Francis
2023-06-14 1:19 ` [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Alistair Francis
2023-06-14 1:19 ` [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Alistair Francis
2023-06-14 1:19 ` [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Alistair Francis
2023-06-14 1:19 ` [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition Alistair Francis
2023-06-14 1:19 ` [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Alistair Francis
2023-06-14 1:19 ` [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs Alistair Francis
2023-06-14 1:19 ` [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address Alistair Francis
2023-06-14 1:19 ` [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes Alistair Francis
2023-06-14 1:19 ` [PULL 34/60] target/riscv: smstateen check for fcsr Alistair Francis
2023-06-14 1:19 ` [PULL 35/60] target/riscv: Reuse tb->flags.FS Alistair Francis
2023-06-14 1:19 ` [PULL 36/60] target/riscv: smstateen knobs Alistair Francis
2023-06-14 1:19 ` [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer Alistair Francis
2023-06-14 1:19 ` [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Alistair Francis
2023-06-14 1:19 ` [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Alistair Francis
2023-06-14 1:19 ` [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
2023-06-14 1:19 ` [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions Alistair Francis
2023-06-14 1:19 ` [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Alistair Francis
2023-06-14 1:20 ` [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters Alistair Francis
2023-06-14 1:20 ` [PULL 44/60] disas/riscv.c: Remove redundant parentheses Alistair Francis
2023-06-14 1:20 ` [PULL 45/60] target/riscv: Fix target address to update badaddr Alistair Francis
2023-06-14 1:20 ` [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements Alistair Francis
2023-06-14 1:20 ` [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc Alistair Francis
2023-06-14 1:20 ` [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff Alistair Francis
2023-06-14 1:20 ` [PULL 50/60] target/riscv: Enable PC-relative translation Alistair Francis
2023-06-14 1:20 ` [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" Alistair Francis
2023-06-14 1:20 ` [PULL 53/60] riscv/virt: Support using pflash via -blockdev option Alistair Francis
2023-06-14 1:20 ` [PULL 54/60] docs/system: riscv: Add pflash usage details Alistair Francis
2023-06-14 1:20 ` [PULL 55/60] util/log: Add vector registers to log Alistair Francis
2023-06-14 1:20 ` [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask Alistair Francis
2023-06-14 1:20 ` [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE Alistair Francis
2023-06-14 1:20 ` [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements Alistair Francis
2023-06-14 1:20 ` [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP Alistair Francis
2023-06-14 1:20 ` [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Alistair Francis
2023-06-14 4:39 ` [PULL 00/60] riscv-to-apply queue Richard Henderson
2023-06-14 12:17 ` Michael Tokarev
2023-06-15 4:03 ` Alistair Francis
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