From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Rob Bradford <rbradford@rivosinc.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 5/5] target/riscv: Fix LMUL check to use VLEN
Date: Wed, 19 Jul 2023 14:45:38 +1000 [thread overview]
Message-ID: <20230719044538.2013401-6-alistair.francis@wdc.com> (raw)
In-Reply-To: <20230719044538.2013401-1-alistair.francis@wdc.com>
From: Rob Bradford <rbradford@rivosinc.com>
The previous check was failing with:
VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a
valid combination.
Fix the check to allow valid combinations when VLEN is a multiple of
ELEN.
From the specification:
"In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where
SEWMIN is the narrowest supported SEW value and ELEN is the widest
supported SEW value. In the standard extensions, SEWMIN=8. For standard
vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be
supported. For standard vector extensions with ELEN=64, fractional LMULs
of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification
it makes clear that VLEN>=ELEN.
From inspection this new check allows:
VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8
VLEN=ELEN=32 1/2, 1/4 for SEW >=8
Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions")
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230718131316.12283-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cfacf2ebba..4d06754826 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if (lmul & 4) {
- /* Fractional LMUL. */
+ /* Fractional LMUL - check LMUL * VLEN >= SEW */
if (lmul == 4 ||
- cpu->cfg.elen >> (8 - lmul) < sew) {
+ cpu->cfg.vlen >> (8 - lmul) < sew) {
vill = true;
}
}
--
2.40.1
next prev parent reply other threads:[~2023-07-19 4:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis
2023-07-19 4:45 ` [PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section Alistair Francis
2023-07-19 4:45 ` [PULL 2/5] riscv/disas: Fix disas output of upper immediates Alistair Francis
2023-07-19 4:45 ` [PULL 3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf Alistair Francis
2023-07-19 4:45 ` [PULL 4/5] hw/riscv: Fix typo field in error_report Alistair Francis
2023-07-19 4:45 ` Alistair Francis [this message]
2023-07-19 19:30 ` [PULL 0/5] riscv-to-apply queue Peter Maydell
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