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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Sunil V L <sunilvl@ventanamicro.com>,
	Igor Mammedov <imammedo@redhat.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"Michael S . Tsirkin" <mst@redhat.com>
Subject: [PULL 22/65] hw/riscv/virt: Update GPEX MMIO related properties
Date: Wed, 10 Jan 2024 18:56:50 +1000	[thread overview]
Message-ID: <20240110085733.1607526-23-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com>

From: Sunil V L <sunilvl@ventanamicro.com>

Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-12-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  1 +
 hw/riscv/virt.c         | 47 ++++++++++++++++++++++++++++-------------
 2 files changed, 33 insertions(+), 15 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 5b03575ed3..f89790fd58 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -61,6 +61,7 @@ struct RISCVVirtState {
     char *oem_table_id;
     OnOffAuto acpi;
     const MemMapEntry *memmap;
+    struct GPEXHost *gpex_host;
 };
 
 enum {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9e7629c51c..a7c4c3508e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1054,21 +1054,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
 }
 
 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-                                          hwaddr ecam_base, hwaddr ecam_size,
-                                          hwaddr mmio_base, hwaddr mmio_size,
-                                          hwaddr high_mmio_base,
-                                          hwaddr high_mmio_size,
-                                          hwaddr pio_base,
-                                          DeviceState *irqchip)
+                                          DeviceState *irqchip,
+                                          RISCVVirtState *s)
 {
     DeviceState *dev;
     MemoryRegion *ecam_alias, *ecam_reg;
     MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+    hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
+    hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
+    hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
+    hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
+    hwaddr high_mmio_base = virt_high_pcie_memmap.base;
+    hwaddr high_mmio_size = virt_high_pcie_memmap.size;
+    hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
+    hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
     qemu_irq irq;
     int i;
 
     dev = qdev_new(TYPE_GPEX_HOST);
 
+    /* Set GPEX object properties for the virt machine */
+    object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
+                            ecam_base, NULL);
+    object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
+                            ecam_size, NULL);
+    object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+                             PCI_HOST_BELOW_4G_MMIO_BASE,
+                             mmio_base, NULL);
+    object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE,
+                            mmio_size, NULL);
+    object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+                             PCI_HOST_ABOVE_4G_MMIO_BASE,
+                             high_mmio_base, NULL);
+    object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE,
+                            high_mmio_size, NULL);
+    object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
+                            pio_base, NULL);
+    object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
+                            pio_size, NULL);
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     ecam_alias = g_new0(MemoryRegion, 1);
@@ -1099,6 +1123,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
     }
 
+    GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
     return dev;
 }
 
@@ -1494,15 +1519,7 @@ static void virt_machine_init(MachineState *machine)
             qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
     }
 
-    gpex_pcie_init(system_memory,
-                   memmap[VIRT_PCIE_ECAM].base,
-                   memmap[VIRT_PCIE_ECAM].size,
-                   memmap[VIRT_PCIE_MMIO].base,
-                   memmap[VIRT_PCIE_MMIO].size,
-                   virt_high_pcie_memmap.base,
-                   virt_high_pcie_memmap.size,
-                   memmap[VIRT_PCIE_PIO].base,
-                   pcie_irqchip);
+    gpex_pcie_init(system_memory, pcie_irqchip, s);
 
     create_platform_bus(s, mmio_irqchip);
 
-- 
2.43.0



  parent reply	other threads:[~2024-01-10  9:09 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10  8:56 [PULL 00/65] riscv-to-apply queue Alistair Francis
2024-01-10  8:56 ` [PULL 01/65] target/riscv: Add vill check for whole vector register move instructions Alistair Francis
2024-01-10  8:56 ` [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew Alistair Francis
2024-01-10  8:56 ` [PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check Alistair Francis
2024-01-10  8:56 ` [PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV Alistair Francis
2024-01-10  8:56 ` [PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 Alistair Francis
2024-01-10  8:56 ` [PULL 06/65] target/riscv/cpu.c: fix machine IDs getters Alistair Francis
2024-01-10  8:56 ` [PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 Alistair Francis
2024-01-10  8:56 ` [PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 Alistair Francis
2024-01-10  8:56 ` [PULL 09/65] target/riscv/kvm: change timer regs size " Alistair Francis
2024-01-10  8:56 ` [PULL 10/65] target/riscv/kvm: add RISCV_CONFIG_REG() Alistair Francis
2024-01-10  8:56 ` [PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() Alistair Francis
2024-01-10  8:56 ` [PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Alistair Francis
2024-01-10  8:56 ` [PULL 13/65] hw/arm/virt-acpi-build.c: Migrate virtio " Alistair Francis
2024-01-10  8:56 ` [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT Alistair Francis
2024-01-10  8:56 ` [PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public Alistair Francis
2024-01-10  8:56 ` [PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Alistair Francis
2024-01-10  8:56 ` [PULL 17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Alistair Francis
2024-01-10  8:56 ` [PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC " Alistair Francis
2024-01-10  8:56 ` [PULL 19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Alistair Francis
2024-01-10  8:56 ` [PULL 20/65] hw/riscv/virt-acpi-build.c: Add MMU node " Alistair Francis
2024-01-10  8:56 ` [PULL 21/65] hw/pci-host/gpex: Define properties for MMIO ranges Alistair Francis
2024-01-10  8:56 ` Alistair Francis [this message]
2024-01-10  8:56 ` [PULL 23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Alistair Francis
2024-01-10  8:56 ` [PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Alistair Francis
2024-01-10  8:56 ` [PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC Alistair Francis
2024-01-10  8:56 ` [PULL 26/65] target/riscv: Add support for Zacas extension Alistair Francis
2024-01-10  8:56 ` [PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions Alistair Francis
2024-01-10  8:56 ` [PULL 28/65] docs/system/riscv: document acpi parameter of virt machine Alistair Francis
2024-01-10  8:56 ` [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU Alistair Francis
2024-01-10  8:56 ` [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks Alistair Francis
2024-01-10  8:56 ` [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions Alistair Francis
2024-01-10  8:57 ` [PULL 32/65] target/riscv: add rv64i CPU Alistair Francis
2024-01-10  8:57 ` [PULL 33/65] target/riscv: add zicbop extension flag Alistair Francis
2024-01-10  8:57 ` [PULL 34/65] target/riscv/tcg: add 'zic64b' support Alistair Francis
2024-01-10  8:57 ` [PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Alistair Francis
2024-01-10  8:57 ` [PULL 36/65] target/riscv: add rva22u64 profile definition Alistair Francis
2024-01-10  8:57 ` [PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable Alistair Francis
2024-01-10  8:57 ` [PULL 38/65] target/riscv/tcg: add user flag for profile support Alistair Francis
2024-01-10  8:57 ` [PULL 39/65] target/riscv/tcg: add MISA user options hash Alistair Francis
2024-01-10  8:57 ` [PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit() Alistair Francis
2024-01-10  8:57 ` [PULL 41/65] target/riscv/tcg: handle profile MISA bits Alistair Francis
2024-01-10  8:57 ` [PULL 42/65] target/riscv/tcg: add hash table insert helpers Alistair Francis
2024-01-10  8:57 ` [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits Alistair Francis
2024-01-10  8:57 ` [PULL 44/65] target/riscv/tcg: validate profiles during finalize Alistair Francis
2024-01-10  8:57 ` [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Alistair Francis
2024-01-10  8:57 ` [PULL 46/65] target/riscv: add 'rva22u64' CPU Alistair Francis
2024-01-10  8:57 ` [PULL 47/65] target/riscv: implement svade Alistair Francis
2024-01-10  8:57 ` [PULL 48/65] target/riscv: add priv ver restriction to profiles Alistair Francis
2024-01-10  8:57 ` [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier Alistair Francis
2024-01-10  8:57 ` [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit() Alistair Francis
2024-01-10  8:57 ` [PULL 51/65] target/riscv: add satp_mode profile support Alistair Francis
2024-01-10  8:57 ` [PULL 52/65] target/riscv: add 'parent' in profile description Alistair Francis
2024-01-10  8:57 ` [PULL 53/65] target/riscv: add RVA22S64 profile Alistair Francis
2024-01-10  8:57 ` [PULL 54/65] target/riscv: add rva22s64 cpu Alistair Francis
2024-01-10  8:57 ` [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket Alistair Francis
2024-01-10  8:57 ` [PULL 56/65] linux-headers: Update to Linux v6.7-rc5 Alistair Francis
2024-01-10  8:57 ` [PULL 57/65] linux-headers: riscv: add ptrace.h Alistair Francis
2024-01-10  8:57 ` [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() Alistair Francis
2024-01-10  8:57 ` [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs Alistair Francis
2024-01-10  8:57 ` [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions Alistair Francis
2024-01-10  8:57 ` [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4 Alistair Francis
2024-01-10  8:57 ` [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0 Alistair Francis
2024-01-10  8:57 ` [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct Alistair Francis
2024-01-10  8:57 ` [PULL 64/65] target/riscv: Don't adjust vscause for exceptions Alistair Francis
2024-01-10  8:57 ` [PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset Alistair Francis
2024-01-10 16:21 ` [PULL 00/65] riscv-to-apply queue Peter Maydell

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