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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Ivan Klokov <ivan.klokov@syntacore.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32
Date: Wed, 10 Jan 2024 18:56:33 +1000	[thread overview]
Message-ID: <20240110085733.1607526-6-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com>

From: Ivan Klokov <ivan.klokov@syntacore.com>

The Sv32 page-based virtual-memory scheme described in RISCV privileged
spec Section 5.3 supports 34-bit physical addresses for RV32, so the
PMP scheme must support addresses wider than XLEN for RV32. However,
PMP address register format is still 32 bit wide.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231123091214.20312-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/pmp.h |  8 ++++----
 target/riscv/pmp.c | 26 ++++++++++++--------------
 2 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 9af8614cd4..f5c10ce85c 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -53,8 +53,8 @@ typedef struct {
 } pmp_entry_t;
 
 typedef struct {
-    target_ulong sa;
-    target_ulong ea;
+    hwaddr sa;
+    hwaddr ea;
 } pmp_addr_t;
 
 typedef struct {
@@ -73,11 +73,11 @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
                        target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
-bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
                         target_ulong size, pmp_priv_t privs,
                         pmp_priv_t *allowed_privs,
                         target_ulong mode);
-target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr);
+target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
 uint32_t pmp_get_num_rules(CPURISCVState *env);
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 162e88a90a..dff9512c3f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -150,8 +150,7 @@ void pmp_unlock_entries(CPURISCVState *env)
     }
 }
 
-static void pmp_decode_napot(target_ulong a, target_ulong *sa,
-                             target_ulong *ea)
+static void pmp_decode_napot(hwaddr a, hwaddr *sa, hwaddr *ea)
 {
     /*
      * aaaa...aaa0   8-byte NAPOT range
@@ -173,8 +172,8 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
     uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
     target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
     target_ulong prev_addr = 0u;
-    target_ulong sa = 0u;
-    target_ulong ea = 0u;
+    hwaddr sa = 0u;
+    hwaddr ea = 0u;
 
     if (pmp_index >= 1u) {
         prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg;
@@ -227,8 +226,7 @@ void pmp_update_rule_nums(CPURISCVState *env)
     }
 }
 
-static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
-                           target_ulong addr)
+static int pmp_is_in_range(CPURISCVState *env, int pmp_index, hwaddr addr)
 {
     int result = 0;
 
@@ -305,14 +303,14 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t privs,
  * Return true if a pmp rule match or default match
  * Return false if no match
  */
-bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
                         target_ulong size, pmp_priv_t privs,
                         pmp_priv_t *allowed_privs, target_ulong mode)
 {
     int i = 0;
     int pmp_size = 0;
-    target_ulong s = 0;
-    target_ulong e = 0;
+    hwaddr s = 0;
+    hwaddr e = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
@@ -624,12 +622,12 @@ target_ulong mseccfg_csr_read(CPURISCVState *env)
  * To avoid this we return a size of 1 (which means no caching) if the PMP
  * region only covers partial of the TLB page.
  */
-target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr)
+target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
 {
-    target_ulong pmp_sa;
-    target_ulong pmp_ea;
-    target_ulong tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
-    target_ulong tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
+    hwaddr pmp_sa;
+    hwaddr pmp_ea;
+    hwaddr tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
+    hwaddr tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
     int i;
 
     /*
-- 
2.43.0



  parent reply	other threads:[~2024-01-10  8:58 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10  8:56 [PULL 00/65] riscv-to-apply queue Alistair Francis
2024-01-10  8:56 ` [PULL 01/65] target/riscv: Add vill check for whole vector register move instructions Alistair Francis
2024-01-10  8:56 ` [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew Alistair Francis
2024-01-10  8:56 ` [PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check Alistair Francis
2024-01-10  8:56 ` [PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV Alistair Francis
2024-01-10  8:56 ` Alistair Francis [this message]
2024-01-10  8:56 ` [PULL 06/65] target/riscv/cpu.c: fix machine IDs getters Alistair Francis
2024-01-10  8:56 ` [PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 Alistair Francis
2024-01-10  8:56 ` [PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 Alistair Francis
2024-01-10  8:56 ` [PULL 09/65] target/riscv/kvm: change timer regs size " Alistair Francis
2024-01-10  8:56 ` [PULL 10/65] target/riscv/kvm: add RISCV_CONFIG_REG() Alistair Francis
2024-01-10  8:56 ` [PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() Alistair Francis
2024-01-10  8:56 ` [PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Alistair Francis
2024-01-10  8:56 ` [PULL 13/65] hw/arm/virt-acpi-build.c: Migrate virtio " Alistair Francis
2024-01-10  8:56 ` [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT Alistair Francis
2024-01-10  8:56 ` [PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public Alistair Francis
2024-01-10  8:56 ` [PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Alistair Francis
2024-01-10  8:56 ` [PULL 17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Alistair Francis
2024-01-10  8:56 ` [PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC " Alistair Francis
2024-01-10  8:56 ` [PULL 19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Alistair Francis
2024-01-10  8:56 ` [PULL 20/65] hw/riscv/virt-acpi-build.c: Add MMU node " Alistair Francis
2024-01-10  8:56 ` [PULL 21/65] hw/pci-host/gpex: Define properties for MMIO ranges Alistair Francis
2024-01-10  8:56 ` [PULL 22/65] hw/riscv/virt: Update GPEX MMIO related properties Alistair Francis
2024-01-10  8:56 ` [PULL 23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Alistair Francis
2024-01-10  8:56 ` [PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Alistair Francis
2024-01-10  8:56 ` [PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC Alistair Francis
2024-01-10  8:56 ` [PULL 26/65] target/riscv: Add support for Zacas extension Alistair Francis
2024-01-10  8:56 ` [PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions Alistair Francis
2024-01-10  8:56 ` [PULL 28/65] docs/system/riscv: document acpi parameter of virt machine Alistair Francis
2024-01-10  8:56 ` [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU Alistair Francis
2024-01-10  8:56 ` [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks Alistair Francis
2024-01-10  8:56 ` [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions Alistair Francis
2024-01-10  8:57 ` [PULL 32/65] target/riscv: add rv64i CPU Alistair Francis
2024-01-10  8:57 ` [PULL 33/65] target/riscv: add zicbop extension flag Alistair Francis
2024-01-10  8:57 ` [PULL 34/65] target/riscv/tcg: add 'zic64b' support Alistair Francis
2024-01-10  8:57 ` [PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Alistair Francis
2024-01-10  8:57 ` [PULL 36/65] target/riscv: add rva22u64 profile definition Alistair Francis
2024-01-10  8:57 ` [PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable Alistair Francis
2024-01-10  8:57 ` [PULL 38/65] target/riscv/tcg: add user flag for profile support Alistair Francis
2024-01-10  8:57 ` [PULL 39/65] target/riscv/tcg: add MISA user options hash Alistair Francis
2024-01-10  8:57 ` [PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit() Alistair Francis
2024-01-10  8:57 ` [PULL 41/65] target/riscv/tcg: handle profile MISA bits Alistair Francis
2024-01-10  8:57 ` [PULL 42/65] target/riscv/tcg: add hash table insert helpers Alistair Francis
2024-01-10  8:57 ` [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits Alistair Francis
2024-01-10  8:57 ` [PULL 44/65] target/riscv/tcg: validate profiles during finalize Alistair Francis
2024-01-10  8:57 ` [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Alistair Francis
2024-01-10  8:57 ` [PULL 46/65] target/riscv: add 'rva22u64' CPU Alistair Francis
2024-01-10  8:57 ` [PULL 47/65] target/riscv: implement svade Alistair Francis
2024-01-10  8:57 ` [PULL 48/65] target/riscv: add priv ver restriction to profiles Alistair Francis
2024-01-10  8:57 ` [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier Alistair Francis
2024-01-10  8:57 ` [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit() Alistair Francis
2024-01-10  8:57 ` [PULL 51/65] target/riscv: add satp_mode profile support Alistair Francis
2024-01-10  8:57 ` [PULL 52/65] target/riscv: add 'parent' in profile description Alistair Francis
2024-01-10  8:57 ` [PULL 53/65] target/riscv: add RVA22S64 profile Alistair Francis
2024-01-10  8:57 ` [PULL 54/65] target/riscv: add rva22s64 cpu Alistair Francis
2024-01-10  8:57 ` [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket Alistair Francis
2024-01-10  8:57 ` [PULL 56/65] linux-headers: Update to Linux v6.7-rc5 Alistair Francis
2024-01-10  8:57 ` [PULL 57/65] linux-headers: riscv: add ptrace.h Alistair Francis
2024-01-10  8:57 ` [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() Alistair Francis
2024-01-10  8:57 ` [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs Alistair Francis
2024-01-10  8:57 ` [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions Alistair Francis
2024-01-10  8:57 ` [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4 Alistair Francis
2024-01-10  8:57 ` [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0 Alistair Francis
2024-01-10  8:57 ` [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct Alistair Francis
2024-01-10  8:57 ` [PULL 64/65] target/riscv: Don't adjust vscause for exceptions Alistair Francis
2024-01-10  8:57 ` [PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset Alistair Francis
2024-01-10 16:21 ` [PULL 00/65] riscv-to-apply queue Peter Maydell

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