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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bmeng@tinylab.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 60/65] docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
Date: Wed, 10 Jan 2024 18:57:28 +1000	[thread overview]
Message-ID: <20240110085733.1607526-61-alistair.francis@wdc.com> (raw)
In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com>

From: Bin Meng <bmeng@tinylab.org>

Currently, the documentation outlines the process for building the
S-mode U-Boot image using `make menuconfig` and manual actions within
the menuconfig UI. However, this approach is fragile due to Kconfig
options potentially changing across different releases. For example,
CONFIG_OF_PRIOR_STAGE has been replaced by CONFIG_BOARD since v2022.01
release, and CONFIG_TEXT_BASE has been moved to the 'General setup'
menu from the 'Boot options' menu in v2024.01 release.

This update aims to make the S-mode U-Boot image build instructions
future-proof. It leverages the 'config' script provided in the U-Boot
source tree to edit the .config file, followed by a `make olddefconfig`.

Validated with U-Boot v2024.01 release.

Signed-off-by: Bin Meng <bmeng@tinylab.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240104071523.273702-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/sifive_u.rst | 33 ++++++++++++---------------------
 1 file changed, 12 insertions(+), 21 deletions(-)

diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 7b166567f9..8f55ae8e31 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -210,7 +210,7 @@ command line options with ``qemu-system-riscv32``.
 Running U-Boot
 --------------
 
-U-Boot mainline v2021.07 release is tested at the time of writing. To build a
+U-Boot mainline v2024.01 release is tested at the time of writing. To build a
 U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine, use
 the sifive_unleashed_defconfig with similar commands as described above for
 Linux:
@@ -325,15 +325,10 @@ configuration of U-Boot:
 
   $ export CROSS_COMPILE=riscv64-linux-
   $ make sifive_unleashed_defconfig
-  $ make menuconfig
-
-then manually select the following configuration:
-
-  * Device Tree Control ---> Provider of DTB for DT Control ---> Prior Stage bootloader DTB
-
-and unselect the following configuration:
-
-  * Library routines ---> Allow access to binman information in the device tree
+  $ ./scripts/config --enable OF_BOARD
+  $ ./scripts/config --disable BINMAN_FDT
+  $ ./scripts/config --disable SPL
+  $ make olddefconfig
 
 This changes U-Boot to use the QEMU generated device tree blob, and bypass
 running the U-Boot SPL stage.
@@ -352,17 +347,13 @@ It's possible to create a 32-bit U-Boot S-mode image as well.
 
   $ export CROSS_COMPILE=riscv64-linux-
   $ make sifive_unleashed_defconfig
-  $ make menuconfig
-
-then manually update the following configuration in U-Boot:
-
-  * Device Tree Control ---> Provider of DTB for DT Control ---> Prior Stage bootloader DTB
-  * RISC-V architecture ---> Base ISA ---> RV32I
-  * Boot options ---> Boot images ---> Text Base ---> 0x80400000
-
-and unselect the following configuration:
-
-  * Library routines ---> Allow access to binman information in the device tree
+  $ ./scripts/config --disable ARCH_RV64I
+  $ ./scripts/config --enable ARCH_RV32I
+  $ ./scripts/config --set-val TEXT_BASE 0x80400000
+  $ ./scripts/config --enable OF_BOARD
+  $ ./scripts/config --disable BINMAN_FDT
+  $ ./scripts/config --disable SPL
+  $ make olddefconfig
 
 Use the same command line options to boot the 32-bit U-Boot S-mode image:
 
-- 
2.43.0



  parent reply	other threads:[~2024-01-10  9:07 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10  8:56 [PULL 00/65] riscv-to-apply queue Alistair Francis
2024-01-10  8:56 ` [PULL 01/65] target/riscv: Add vill check for whole vector register move instructions Alistair Francis
2024-01-10  8:56 ` [PULL 02/65] target/riscv: The whole vector register move instructions depend on vsew Alistair Francis
2024-01-10  8:56 ` [PULL 03/65] target/riscv: Fix th.dcache.cval1 priviledge check Alistair Francis
2024-01-10  8:56 ` [PULL 04/65] target/riscv: Not allow write mstatus_vs without RVV Alistair Francis
2024-01-10  8:56 ` [PULL 05/65] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 Alistair Francis
2024-01-10  8:56 ` [PULL 06/65] target/riscv/cpu.c: fix machine IDs getters Alistair Francis
2024-01-10  8:56 ` [PULL 07/65] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 Alistair Francis
2024-01-10  8:56 ` [PULL 08/65] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 Alistair Francis
2024-01-10  8:56 ` [PULL 09/65] target/riscv/kvm: change timer regs size " Alistair Francis
2024-01-10  8:56 ` [PULL 10/65] target/riscv/kvm: add RISCV_CONFIG_REG() Alistair Francis
2024-01-10  8:56 ` [PULL 11/65] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() Alistair Francis
2024-01-10  8:56 ` [PULL 12/65] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Alistair Francis
2024-01-10  8:56 ` [PULL 13/65] hw/arm/virt-acpi-build.c: Migrate virtio " Alistair Francis
2024-01-10  8:56 ` [PULL 14/65] hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT Alistair Francis
2024-01-10  8:56 ` [PULL 15/65] hw/riscv: virt: Make few IMSIC macros and functions public Alistair Francis
2024-01-10  8:56 ` [PULL 16/65] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Alistair Francis
2024-01-10  8:56 ` [PULL 17/65] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Alistair Francis
2024-01-10  8:56 ` [PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC " Alistair Francis
2024-01-10  8:56 ` [PULL 19/65] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Alistair Francis
2024-01-10  8:56 ` [PULL 20/65] hw/riscv/virt-acpi-build.c: Add MMU node " Alistair Francis
2024-01-10  8:56 ` [PULL 21/65] hw/pci-host/gpex: Define properties for MMIO ranges Alistair Francis
2024-01-10  8:56 ` [PULL 22/65] hw/riscv/virt: Update GPEX MMIO related properties Alistair Francis
2024-01-10  8:56 ` [PULL 23/65] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Alistair Francis
2024-01-10  8:56 ` [PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Alistair Francis
2024-01-10  8:56 ` [PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC Alistair Francis
2024-01-10  8:56 ` [PULL 26/65] target/riscv: Add support for Zacas extension Alistair Francis
2024-01-10  8:56 ` [PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions Alistair Francis
2024-01-10  8:56 ` [PULL 28/65] docs/system/riscv: document acpi parameter of virt machine Alistair Francis
2024-01-10  8:56 ` [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU Alistair Francis
2024-01-10  8:56 ` [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks Alistair Francis
2024-01-10  8:56 ` [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions Alistair Francis
2024-01-10  8:57 ` [PULL 32/65] target/riscv: add rv64i CPU Alistair Francis
2024-01-10  8:57 ` [PULL 33/65] target/riscv: add zicbop extension flag Alistair Francis
2024-01-10  8:57 ` [PULL 34/65] target/riscv/tcg: add 'zic64b' support Alistair Francis
2024-01-10  8:57 ` [PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Alistair Francis
2024-01-10  8:57 ` [PULL 36/65] target/riscv: add rva22u64 profile definition Alistair Francis
2024-01-10  8:57 ` [PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable Alistair Francis
2024-01-10  8:57 ` [PULL 38/65] target/riscv/tcg: add user flag for profile support Alistair Francis
2024-01-10  8:57 ` [PULL 39/65] target/riscv/tcg: add MISA user options hash Alistair Francis
2024-01-10  8:57 ` [PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit() Alistair Francis
2024-01-10  8:57 ` [PULL 41/65] target/riscv/tcg: handle profile MISA bits Alistair Francis
2024-01-10  8:57 ` [PULL 42/65] target/riscv/tcg: add hash table insert helpers Alistair Francis
2024-01-10  8:57 ` [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits Alistair Francis
2024-01-10  8:57 ` [PULL 44/65] target/riscv/tcg: validate profiles during finalize Alistair Francis
2024-01-10  8:57 ` [PULL 45/65] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Alistair Francis
2024-01-10  8:57 ` [PULL 46/65] target/riscv: add 'rva22u64' CPU Alistair Francis
2024-01-10  8:57 ` [PULL 47/65] target/riscv: implement svade Alistair Francis
2024-01-10  8:57 ` [PULL 48/65] target/riscv: add priv ver restriction to profiles Alistair Francis
2024-01-10  8:57 ` [PULL 49/65] target/riscv/cpu.c: finalize satp_mode earlier Alistair Francis
2024-01-10  8:57 ` [PULL 50/65] target/riscv/cpu.c: add riscv_cpu_is_32bit() Alistair Francis
2024-01-10  8:57 ` [PULL 51/65] target/riscv: add satp_mode profile support Alistair Francis
2024-01-10  8:57 ` [PULL 52/65] target/riscv: add 'parent' in profile description Alistair Francis
2024-01-10  8:57 ` [PULL 53/65] target/riscv: add RVA22S64 profile Alistair Francis
2024-01-10  8:57 ` [PULL 54/65] target/riscv: add rva22s64 cpu Alistair Francis
2024-01-10  8:57 ` [PULL 55/65] target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket Alistair Francis
2024-01-10  8:57 ` [PULL 56/65] linux-headers: Update to Linux v6.7-rc5 Alistair Francis
2024-01-10  8:57 ` [PULL 57/65] linux-headers: riscv: add ptrace.h Alistair Francis
2024-01-10  8:57 ` [PULL 58/65] target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() Alistair Francis
2024-01-10  8:57 ` [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs Alistair Francis
2024-01-10  8:57 ` Alistair Francis [this message]
2024-01-10  8:57 ` [PULL 61/65] roms/opensbi: Upgrade from v1.3.1 to v1.4 Alistair Francis
2024-01-10  8:57 ` [PULL 62/65] target/riscv: pmp: Ignore writes when RW=01 and MML=0 Alistair Francis
2024-01-10  8:57 ` [PULL 63/65] target/riscv: Assert that the CSR numbers will be correct Alistair Francis
2024-01-10  8:57 ` [PULL 64/65] target/riscv: Don't adjust vscause for exceptions Alistair Francis
2024-01-10  8:57 ` [PULL 65/65] target/riscv: Ensure mideleg is set correctly on reset Alistair Francis
2024-01-10 16:21 ` [PULL 00/65] riscv-to-apply queue Peter Maydell

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