From: Jason Chien <jason.chien@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions
Date: Wed, 20 Mar 2024 00:23:16 +0800 [thread overview]
Message-ID: <CADr__8onmfjCtzdct2-ptXmM34h1HZVppOq=Fzi1YGigcm4ckQ@mail.gmail.com> (raw)
In-Reply-To: <20240306170855.24341-1-jason.chien@sifive.com>
[-- Attachment #1: Type: text/plain, Size: 1055 bytes --]
Ping. Can anyone review the patches please?
Jason Chien <jason.chien@sifive.com> 於 2024年3月7日 週四 上午1:09寫道:
> This patch series adds the support for Zve32x and Zvx64x and makes vector
> registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
> Jason Chien (5):
> target/riscv: Add support for Zve32x extension
> target/riscv: Expose Zve32x extension to users
> target/riscv: Add support for Zve64x extension
> target/riscv: Expose Zve64x extension to users
> target/riscv: Relax vector register check in RISCV gdbstub
>
> target/riscv/cpu.c | 4 +++
> target/riscv/cpu_cfg.h | 2 ++
> target/riscv/cpu_helper.c | 2 +-
> target/riscv/csr.c | 2 +-
> target/riscv/gdbstub.c | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 4 +--
> target/riscv/tcg/tcg-cpu.c | 33 ++++++++++++++-----------
> 7 files changed, 30 insertions(+), 19 deletions(-)
>
> --
> 2.43.2
>
>
[-- Attachment #2: Type: text/html, Size: 1453 bytes --]
prev parent reply other threads:[~2024-03-19 16:23 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 17:08 [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions Jason Chien
2024-03-06 17:08 ` [PATCH 1/5] target/riscv: Add support for Zve32x extension Jason Chien
2024-03-19 16:23 ` Jason Chien
2024-03-19 21:19 ` Daniel Henrique Barboza
2024-03-21 7:06 ` Jason Chien
2024-03-06 17:08 ` [PATCH 2/5] target/riscv: Expose Zve32x extension to users Jason Chien
2024-03-06 17:08 ` [PATCH 3/5] target/riscv: Add support for Zve64x extension Jason Chien
2024-03-06 17:08 ` [PATCH 4/5] target/riscv: Expose Zve64x extension to users Jason Chien
2024-03-21 12:20 ` Daniel Henrique Barboza
2024-03-06 17:08 ` [PATCH 5/5] target/riscv: Relax vector register check in RISCV gdbstub Jason Chien
2024-03-19 16:23 ` Jason Chien [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CADr__8onmfjCtzdct2-ptXmM34h1HZVppOq=Fzi1YGigcm4ckQ@mail.gmail.com' \
--to=jason.chien@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).