From: Jason Chien <jason.chien@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Jason Chien <jason.chien@sifive.com>
Subject: [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions
Date: Thu, 7 Mar 2024 01:08:33 +0800 [thread overview]
Message-ID: <20240306170855.24341-1-jason.chien@sifive.com> (raw)
This patch series adds the support for Zve32x and Zvx64x and makes vector
registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
Jason Chien (5):
target/riscv: Add support for Zve32x extension
target/riscv: Expose Zve32x extension to users
target/riscv: Add support for Zve64x extension
target/riscv: Expose Zve64x extension to users
target/riscv: Relax vector register check in RISCV gdbstub
target/riscv/cpu.c | 4 +++
target/riscv/cpu_cfg.h | 2 ++
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 2 +-
target/riscv/gdbstub.c | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 +--
target/riscv/tcg/tcg-cpu.c | 33 ++++++++++++++-----------
7 files changed, 30 insertions(+), 19 deletions(-)
--
2.43.2
next reply other threads:[~2024-03-06 17:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-06 17:08 Jason Chien [this message]
2024-03-06 17:08 ` [PATCH 1/5] target/riscv: Add support for Zve32x extension Jason Chien
2024-03-19 16:23 ` Jason Chien
2024-03-19 21:19 ` Daniel Henrique Barboza
2024-03-21 7:06 ` Jason Chien
2024-03-06 17:08 ` [PATCH 2/5] target/riscv: Expose Zve32x extension to users Jason Chien
2024-03-06 17:08 ` [PATCH 3/5] target/riscv: Add support for Zve64x extension Jason Chien
2024-03-06 17:08 ` [PATCH 4/5] target/riscv: Expose Zve64x extension to users Jason Chien
2024-03-21 12:20 ` Daniel Henrique Barboza
2024-03-06 17:08 ` [PATCH 5/5] target/riscv: Relax vector register check in RISCV gdbstub Jason Chien
2024-03-19 16:23 ` [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions Jason Chien
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