Re: [PATCH 1/5] target/riscv: Add support for Zve32x extension

[Jason Chien <jason.chien@sifive.com>]

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I will re-send shortly. Thanks.

Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年3月20日 週三
上午5:19寫道：

> Hi Jason,
>
> Care to re-send please? The patches don't apply to neither
> riscv-to-apply.next
> nor master.
>
>
> Thanks,
>
> Daniel
>
> On 3/19/24 13:23, Jason Chien wrote:
> > Ping. Can anyone review the patches please?
> >
> > Jason Chien <jason.chien@sifive.com <mailto:jason.chien@sifive.com>> 於
> 2024年3月7日 週四 上午1:09寫道：
> >
> >     Add support for Zve32x extension and replace some checks for Zve32f
> with
> >     Zve32x, since Zve32f depends on Zve32x.
> >
> >     Signed-off-by: Jason Chien <jason.chien@sifive.com <mailto:
> jason.chien@sifive.com>>
> >     Reviewed-by: Frank Chang <frank.chang@sifive.com <mailto:
> frank.chang@sifive.com>>
> >     Reviewed-by: Max Chou <max.chou@sifive.com <mailto:
> max.chou@sifive.com>>
> >     ---
> >       target/riscv/cpu.c                      |  1 +
> >       target/riscv/cpu_cfg.h                  |  1 +
> >       target/riscv/cpu_helper.c               |  2 +-
> >       target/riscv/csr.c                      |  2 +-
> >       target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
> >       target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
> >       6 files changed, 14 insertions(+), 12 deletions(-)
> >
> >     diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >     index fd0c7efdda..10ccae3323 100644
> >     --- a/target/riscv/cpu.c
> >     +++ b/target/riscv/cpu.c
> >     @@ -152,6 +152,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> >           ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
> >           ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
> >           ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
> >     +    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
> >           ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
> >           ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
> >           ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0,
> ext_zvfbfmin),
> >     diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> >     index be39870691..beb3d10213 100644
> >     --- a/target/riscv/cpu_cfg.h
> >     +++ b/target/riscv/cpu_cfg.h
> >     @@ -90,6 +90,7 @@ struct RISCVCPUConfig {
> >           bool ext_zhinx;
> >           bool ext_zhinxmin;
> >           bool ext_zve32f;
> >     +    bool ext_zve32x;
> >           bool ext_zve64f;
> >           bool ext_zve64d;
> >           bool ext_zvbb;
> >     diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >     index c994a72634..ebbe56d9a2 100644
> >     --- a/target/riscv/cpu_helper.c
> >     +++ b/target/riscv/cpu_helper.c
> >     @@ -72,7 +72,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
> vaddr *pc,
> >           *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> >           *cs_base = 0;
> >
> >     -    if (cpu->cfg.ext_zve32f) {
> >     +    if (cpu->cfg.ext_zve32x) {
> >               /*
> >                * If env->vl equals to VLMAX, we can use generic vector
> operation
> >                * expanders (GVEC) to accerlate the vector operations.
> >     diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >     index 726096444f..d96feea5d3 100644
> >     --- a/target/riscv/csr.c
> >     +++ b/target/riscv/csr.c
> >     @@ -93,7 +93,7 @@ static RISCVException fs(CPURISCVState *env, int
> csrno)
> >
> >       static RISCVException vs(CPURISCVState *env, int csrno)
> >       {
> >     -    if (riscv_cpu_cfg(env)->ext_zve32f) {
> >     +    if (riscv_cpu_cfg(env)->ext_zve32x) {
> >       #if !defined(CONFIG_USER_ONLY)
> >               if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
> >                   return RISCV_EXCP_ILLEGAL_INST;
> >     diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> >     index 9e101ab434..f00f1ee886 100644
> >     --- a/target/riscv/insn_trans/trans_rvv.c.inc
> >     +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> >     @@ -149,7 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd,
> int rs1, TCGv s2)
> >       {
> >           TCGv s1, dst;
> >
> >     -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
> >     +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
> >               return false;
> >           }
> >
> >     @@ -179,7 +179,7 @@ static bool do_vsetivli(DisasContext *s, int rd,
> TCGv s1, TCGv s2)
> >       {
> >           TCGv dst;
> >
> >     -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
> >     +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
> >               return false;
> >           }
> >
> >     diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> >     index ab6db817db..ce539528e6 100644
> >     --- a/target/riscv/tcg/tcg-cpu.c
> >     +++ b/target/riscv/tcg/tcg-cpu.c
> >     @@ -501,9 +501,13 @@ void riscv_cpu_validate_set_extensions(RISCVCPU
> *cpu, Error **errp)
> >               return;
> >           }
> >
> >     -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
> >     -        error_setg(errp, "Zve32f/Zve64f extensions require F
> extension");
> >     -        return;
> >     +    /* The Zve32f extension depends on the Zve32x extension */
> >     +    if (cpu->cfg.ext_zve32f) {
> >     +        if (!riscv_has_ext(env, RVF)) {
> >     +            error_setg(errp, "Zve32f/Zve64f extensions require F
> extension");
> >     +            return;
> >     +        }
> >     +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x),
> true);
> >           }
> >
> >           if (cpu->cfg.ext_zvfh) {
> >     @@ -653,13 +657,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU
> *cpu, Error **errp)
> >               cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc),
> true);
> >           }
> >
> >     -    /*
> >     -     * In principle Zve*x would also suffice here, were they
> supported
> >     -     * in qemu
> >     -     */
> >           if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb ||
> cpu->cfg.ext_zvkg ||
> >                cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha ||
> cpu->cfg.ext_zvksed ||
> >     -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
> >     +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
> >               error_setg(errp,
> >                          "Vector crypto extensions require V or Zve*
> extensions");
> >               return;
> >     --
> >     2.43.2
> >
>

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