* [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support
@ 2023-07-18 22:47 Kaiwen Xue
2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Kaiwen Xue @ 2023-07-18 22:47 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Kaiwen Xue, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Atish Kumar Patra, Kaiwen Xue
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. QEMU only calculates dummy cycles and
instructions, so there is no actual means to stop the icount in QEMU. Therefore,
this series only add the read/write behavior of the relevant CSRs such that the
implemented firmware support [2] can work without causing unnecessary illegal
instruction exceptions.
[1] https://github.com/riscv/riscv-smcntrpmf
[2] https://github.com/rivosinc/opensbi/tree/dev/kaiwenx/smcntrpmf_upstream
Kaiwen Xue (3):
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering support
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 6 ++++
target/riscv/cpu_bits.h | 29 ++++++++++++++++
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 73 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 111 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties 2023-07-18 22:47 [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support Kaiwen Xue @ 2023-07-18 22:47 ` Kaiwen Xue 2023-07-19 1:20 ` Weiwei Li 2023-07-18 22:47 ` [PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions Kaiwen Xue 2023-07-18 22:47 ` [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support Kaiwen Xue 2 siblings, 1 reply; 8+ messages in thread From: Kaiwen Xue @ 2023-07-18 22:47 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: Kaiwen Xue, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..31a1862561 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -132,6 +132,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1753,6 +1754,7 @@ static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), + DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..424246cbec 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -69,6 +69,7 @@ struct RISCVCPUConfig { bool ext_zihintpause; bool ext_smstateen; bool ext_sstc; + bool ext_smcntrpmf; bool ext_svadu; bool ext_svinval; bool ext_svnapot; -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties 2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue @ 2023-07-19 1:20 ` Weiwei Li 2023-07-22 0:13 ` Kevin Xue 0 siblings, 1 reply; 8+ messages in thread From: Weiwei Li @ 2023-07-19 1:20 UTC (permalink / raw) To: Kaiwen Xue, qemu-riscv, qemu-devel Cc: liweiwei, Palmer Dabbelt, Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue On 2023/7/19 06:47, Kaiwen Xue wrote: > This adds the properties for ISA extension smcntrpmf. Patches > implementing it will follow. > > Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9339c0241d..31a1862561 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -132,6 +132,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > @@ -1753,6 +1754,7 @@ static Property riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > + DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), Normally, property should be exposed to user at last after the function is implemented. Regards, Weiwei Li > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 2bd9510ba3..424246cbec 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -69,6 +69,7 @@ struct RISCVCPUConfig { > bool ext_zihintpause; > bool ext_smstateen; > bool ext_sstc; > + bool ext_smcntrpmf; > bool ext_svadu; > bool ext_svinval; > bool ext_svnapot; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties 2023-07-19 1:20 ` Weiwei Li @ 2023-07-22 0:13 ` Kevin Xue 0 siblings, 0 replies; 8+ messages in thread From: Kevin Xue @ 2023-07-22 0:13 UTC (permalink / raw) To: Weiwei Li Cc: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue On Tue, Jul 18, 2023 at 6:21 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > > On 2023/7/19 06:47, Kaiwen Xue wrote: > > This adds the properties for ISA extension smcntrpmf. Patches > > implementing it will follow. > > > > Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > --- > > target/riscv/cpu.c | 2 ++ > > target/riscv/cpu_cfg.h | 1 + > > 2 files changed, 3 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 9339c0241d..31a1862561 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -132,6 +132,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > > + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > > @@ -1753,6 +1754,7 @@ static Property riscv_cpu_extensions[] = { > > /* Defaults for standard extensions */ > > DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), > > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > > + DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), > > Normally, property should be exposed to user at last after the function > is implemented. > > Regards, > > Weiwei Li Will do in the next version. Thanks, Kevin > > > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index 2bd9510ba3..424246cbec 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -69,6 +69,7 @@ struct RISCVCPUConfig { > > bool ext_zihintpause; > > bool ext_smstateen; > > bool ext_sstc; > > + bool ext_smcntrpmf; > > bool ext_svadu; > > bool ext_svinval; > > bool ext_svnapot; > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions 2023-07-18 22:47 [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support Kaiwen Xue 2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue @ 2023-07-18 22:47 ` Kaiwen Xue 2023-07-18 22:47 ` [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support Kaiwen Xue 2 siblings, 0 replies; 8+ messages in thread From: Kaiwen Xue @ 2023-07-18 22:47 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: Kaiwen Xue, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> --- target/riscv/cpu.h | 6 ++++++ target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..3cdf5d09f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -283,6 +283,12 @@ struct CPUArchState { target_ulong mcountinhibit; + /* PMU cycle & instret privilege mode filtering */ + target_ulong mcyclecfg; + target_ulong mcyclecfgh; + target_ulong minstretcfg; + target_ulong minstretcfgh; + /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 59f0ffd9e1..0a25fb276b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -401,6 +401,10 @@ /* Machine counter-inhibit register */ #define CSR_MCOUNTINHIBIT 0x320 +/* Machine counter configuration registers */ +#define CSR_MCYCLECFG 0x321 +#define CSR_MINSTRETCFG 0x322 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 @@ -431,6 +435,9 @@ #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f +#define CSR_MCYCLECFGH 0x721 +#define CSR_MINSTRETCFGH 0x722 + #define CSR_MHPMEVENT3H 0x723 #define CSR_MHPMEVENT4H 0x724 #define CSR_MHPMEVENT5H 0x725 @@ -879,6 +886,28 @@ typedef enum RISCVException { /* PMU related bits */ #define MIE_LCOFIE (1 << IRQ_PMU_OVF) +#define MCYCLECFG_BIT_MINH BIT_ULL(62) +#define MCYCLECFGH_BIT_MINH BIT(30) +#define MCYCLECFG_BIT_SINH BIT_ULL(61) +#define MCYCLECFGH_BIT_SINH BIT(29) +#define MCYCLECFG_BIT_UINH BIT_ULL(60) +#define MCYCLECFGH_BIT_UINH BIT(28) +#define MCYCLECFG_BIT_VSINH BIT_ULL(59) +#define MCYCLECFGH_BIT_VSINH BIT(27) +#define MCYCLECFG_BIT_VUINH BIT_ULL(58) +#define MCYCLECFGH_BIT_VUINH BIT(26) + +#define MINSTRETCFG_BIT_MINH BIT_ULL(62) +#define MINSTRETCFGH_BIT_MINH BIT(30) +#define MINSTRETCFG_BIT_SINH BIT_ULL(61) +#define MINSTRETCFGH_BIT_SINH BIT(29) +#define MINSTRETCFG_BIT_UINH BIT_ULL(60) +#define MINSTRETCFGH_BIT_UINH BIT(28) +#define MINSTRETCFG_BIT_VSINH BIT_ULL(59) +#define MINSTRETCFGH_BIT_VSINH BIT(27) +#define MINSTRETCFG_BIT_VUINH BIT_ULL(58) +#define MINSTRETCFGH_BIT_VUINH BIT(26) + #define MHPMEVENT_BIT_OF BIT_ULL(63) #define MHPMEVENTH_BIT_OF BIT(31) #define MHPMEVENT_BIT_MINH BIT_ULL(62) -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support 2023-07-18 22:47 [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support Kaiwen Xue 2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue 2023-07-18 22:47 ` [PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions Kaiwen Xue @ 2023-07-18 22:47 ` Kaiwen Xue 2023-07-19 1:25 ` Weiwei Li 2 siblings, 1 reply; 8+ messages in thread From: Kaiwen Xue @ 2023-07-18 22:47 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: Kaiwen Xue, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> --- target/riscv/csr.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..b1d5e85a79 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -218,6 +218,17 @@ static RISCVException sscofpmf(CPURISCVState *env, int csrno) return RISCV_EXCP_NONE; } +static RISCVException smcntrpmf(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (!cpu->cfg.ext_smcntrpmf) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -800,6 +811,54 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) #else /* CONFIG_USER_ONLY */ +static int read_mcyclecfg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mcyclecfg; + return RISCV_EXCP_NONE; +} + +static int write_mcyclecfg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mcyclecfg = val; + return RISCV_EXCP_NONE; +} + +static int read_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mcyclecfgh; + return RISCV_EXCP_NONE; +} + +static int write_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mcyclecfgh = val; + return RISCV_EXCP_NONE; +} + +static int read_minstretcfg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->minstretcfg; + return RISCV_EXCP_NONE; +} + +static int write_minstretcfg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->minstretcfg = val; + return RISCV_EXCP_NONE; +} + +static int read_minstretcfgh(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->minstretcfgh; + return RISCV_EXCP_NONE; +} + +static int write_minstretcfgh(CPURISCVState *env, int csrno, target_ulong val) +{ + env->minstretcfgh = val; + return RISCV_EXCP_NONE; +} + static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { int evt_index = csrno - CSR_MCOUNTINHIBIT; @@ -4506,6 +4565,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, + [CSR_MCYCLECFG] = { "mcyclecfg", smcntrpmf, read_mcyclecfg, + write_mcyclecfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MINSTRETCFG] = { "minstretcfg", smcntrpmf, read_minstretcfg, + write_minstretcfg, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, write_mhpmevent }, [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, @@ -4565,6 +4631,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, + [CSR_MCYCLECFGH] = { "mcyclecfgh", smcntrpmf, read_mcyclecfgh, + write_mcyclecfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MINSTRETCFGH] = { "minstretcfgh", smcntrpmf, read_minstretcfgh, + write_minstretcfgh, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh, write_mhpmeventh, .min_priv_ver = PRIV_VERSION_1_12_0 }, -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support 2023-07-18 22:47 ` [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support Kaiwen Xue @ 2023-07-19 1:25 ` Weiwei Li 2023-07-22 0:25 ` Kevin Xue 0 siblings, 1 reply; 8+ messages in thread From: Weiwei Li @ 2023-07-19 1:25 UTC (permalink / raw) To: Kaiwen Xue, qemu-riscv, qemu-devel Cc: liweiwei, Palmer Dabbelt, Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue On 2023/7/19 06:47, Kaiwen Xue wrote: > QEMU only calculates dummy cycles and instructions, so there is no > actual means to stop the icount in QEMU. Hence this patch merely adds > the functionality of accessing the cfg registers, and cause no actual > effects on the counting of cycle and instret counters. Maybe you can record/accumulate them when privilege mode changes/switchs. > > Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > --- > target/riscv/csr.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index ea7585329e..b1d5e85a79 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -218,6 +218,17 @@ static RISCVException sscofpmf(CPURISCVState *env, int csrno) > return RISCV_EXCP_NONE; > } > > +static RISCVException smcntrpmf(CPURISCVState *env, int csrno) > +{ > + RISCVCPU *cpu = env_archcpu(env); > + > + if (!cpu->cfg.ext_smcntrpmf) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return RISCV_EXCP_NONE; > +} > + > static RISCVException any(CPURISCVState *env, int csrno) > { > return RISCV_EXCP_NONE; > @@ -800,6 +811,54 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) > > #else /* CONFIG_USER_ONLY */ > > +static int read_mcyclecfg(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->mcyclecfg; > + return RISCV_EXCP_NONE; > +} > + > +static int write_mcyclecfg(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->mcyclecfg = val; > + return RISCV_EXCP_NONE; > +} > + > +static int read_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->mcyclecfgh; > + return RISCV_EXCP_NONE; > +} > + > +static int write_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->mcyclecfgh = val; > + return RISCV_EXCP_NONE; > +} > + > +static int read_minstretcfg(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->minstretcfg; > + return RISCV_EXCP_NONE; > +} > + > +static int write_minstretcfg(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->minstretcfg = val; > + return RISCV_EXCP_NONE; > +} > + > +static int read_minstretcfgh(CPURISCVState *env, int csrno, target_ulong *val) > +{ > + *val = env->minstretcfgh; > + return RISCV_EXCP_NONE; > +} > + > +static int write_minstretcfgh(CPURISCVState *env, int csrno, target_ulong val) > +{ > + env->minstretcfgh = val; > + return RISCV_EXCP_NONE; > +} > + > static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) > { > int evt_index = csrno - CSR_MCOUNTINHIBIT; > @@ -4506,6 +4565,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > write_mcountinhibit, > .min_priv_ver = PRIV_VERSION_1_11_0 }, > > + [CSR_MCYCLECFG] = { "mcyclecfg", smcntrpmf, read_mcyclecfg, > + write_mcyclecfg, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MINSTRETCFG] = { "minstretcfg", smcntrpmf, read_minstretcfg, > + write_minstretcfg, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, > write_mhpmevent }, > [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, > @@ -4565,6 +4631,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, > write_mhpmevent }, > > + [CSR_MCYCLECFGH] = { "mcyclecfgh", smcntrpmf, read_mcyclecfgh, > + write_mcyclecfgh, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MINSTRETCFGH] = { "minstretcfgh", smcntrpmf, read_minstretcfgh, > + write_minstretcfgh, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, This two CSRs are RV32-only, they cannot directly share the same predicate as MCYCLECFG/MINSTRETCFG. Regards, Weiwei Li > + > [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh, > write_mhpmeventh, > .min_priv_ver = PRIV_VERSION_1_12_0 }, ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support 2023-07-19 1:25 ` Weiwei Li @ 2023-07-22 0:25 ` Kevin Xue 0 siblings, 0 replies; 8+ messages in thread From: Kevin Xue @ 2023-07-22 0:25 UTC (permalink / raw) To: Weiwei Li Cc: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei, Atish Kumar Patra, Kaiwen Xue On Tue, Jul 18, 2023 at 6:25 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > > On 2023/7/19 06:47, Kaiwen Xue wrote: > > QEMU only calculates dummy cycles and instructions, so there is no > > actual means to stop the icount in QEMU. Hence this patch merely adds > > the functionality of accessing the cfg registers, and cause no actual > > effects on the counting of cycle and instret counters. > Maybe you can record/accumulate them when privilege mode changes/switchs. Good idea. Will do in the next version as well. - Kevin > > > > Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu> > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > --- > > target/riscv/csr.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 73 insertions(+) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index ea7585329e..b1d5e85a79 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -218,6 +218,17 @@ static RISCVException sscofpmf(CPURISCVState *env, int csrno) > > return RISCV_EXCP_NONE; > > } > > > > +static RISCVException smcntrpmf(CPURISCVState *env, int csrno) > > +{ > > + RISCVCPU *cpu = env_archcpu(env); > > + > > + if (!cpu->cfg.ext_smcntrpmf) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException any(CPURISCVState *env, int csrno) > > { > > return RISCV_EXCP_NONE; > > @@ -800,6 +811,54 @@ static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) > > > > #else /* CONFIG_USER_ONLY */ > > > > +static int read_mcyclecfg(CPURISCVState *env, int csrno, target_ulong *val) > > +{ > > + *val = env->mcyclecfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int write_mcyclecfg(CPURISCVState *env, int csrno, target_ulong val) > > +{ > > + env->mcyclecfg = val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int read_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong *val) > > +{ > > + *val = env->mcyclecfgh; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int write_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong val) > > +{ > > + env->mcyclecfgh = val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int read_minstretcfg(CPURISCVState *env, int csrno, target_ulong *val) > > +{ > > + *val = env->minstretcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int write_minstretcfg(CPURISCVState *env, int csrno, target_ulong val) > > +{ > > + env->minstretcfg = val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int read_minstretcfgh(CPURISCVState *env, int csrno, target_ulong *val) > > +{ > > + *val = env->minstretcfgh; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static int write_minstretcfgh(CPURISCVState *env, int csrno, target_ulong val) > > +{ > > + env->minstretcfgh = val; > > + return RISCV_EXCP_NONE; > > +} > > + > > static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) > > { > > int evt_index = csrno - CSR_MCOUNTINHIBIT; > > @@ -4506,6 +4565,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > write_mcountinhibit, > > .min_priv_ver = PRIV_VERSION_1_11_0 }, > > > > + [CSR_MCYCLECFG] = { "mcyclecfg", smcntrpmf, read_mcyclecfg, > > + write_mcyclecfg, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MINSTRETCFG] = { "minstretcfg", smcntrpmf, read_minstretcfg, > > + write_minstretcfg, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, > > write_mhpmevent }, > > [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, > > @@ -4565,6 +4631,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, > > write_mhpmevent }, > > > > + [CSR_MCYCLECFGH] = { "mcyclecfgh", smcntrpmf, read_mcyclecfgh, > > + write_mcyclecfgh, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MINSTRETCFGH] = { "minstretcfgh", smcntrpmf, read_minstretcfgh, > > + write_minstretcfgh, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > This two CSRs are RV32-only, they cannot directly share the same > predicate as MCYCLECFG/MINSTRETCFG. > > Regards, > > Weiwei Li Thanks for catching this! Seems sscofpmf also reused the sscofpmf() predicate for scountovf and mhpmeventXh. I'll probably turn in another patch for that later on. - Kevin > > > + > > [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh, > > write_mhpmeventh, > > .min_priv_ver = PRIV_VERSION_1_12_0 }, > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-07-22 0:26 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-07-18 22:47 [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support Kaiwen Xue 2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue 2023-07-19 1:20 ` Weiwei Li 2023-07-22 0:13 ` Kevin Xue 2023-07-18 22:47 ` [PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions Kaiwen Xue 2023-07-18 22:47 ` [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support Kaiwen Xue 2023-07-19 1:25 ` Weiwei Li 2023-07-22 0:25 ` Kevin Xue
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