From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-riscv@nongnu.org, Anup Patel <Anup.Patel@wdc.com>,
qemu-devel@nongnu.org, Atish Patra <Atish.Patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
alistair23@gmail.com
Subject: Re: [PATCH v1 16/28] target/riscv: Add hypvervisor trap support
Date: Fri, 20 Sep 2019 07:01:15 -0700 (PDT) [thread overview]
Message-ID: <mhng-5090a31d-34ee-455b-bb77-965a09e5bd94@palmer-si-x1c4> (raw)
In-Reply-To: <f8cb17bfb8abe59261394c36d915c2eabd2f4703.1566603412.git.alistair.francis@wdc.com>
On Fri, 23 Aug 2019 16:38:31 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 4 +--
> target/riscv/cpu_helper.c | 71 +++++++++++++++++++++++++++++++++------
> target/riscv/csr.c | 4 +--
> 3 files changed, 65 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5cee72b726..353fc9a24a 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -513,8 +513,8 @@
> #define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
> #define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
> #define RISCV_EXCP_U_ECALL 0x8
> -#define RISCV_EXCP_S_ECALL 0x9
> -#define RISCV_EXCP_H_ECALL 0xa
> +#define RISCV_EXCP_HS_ECALL 0x9
> +#define RISCV_EXCP_VS_ECALL 0xa
> #define RISCV_EXCP_M_ECALL 0xb
> #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
> #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 8e8b156fc0..17eec6217b 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -668,6 +668,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> + target_ulong s;
>
> /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
> * so we mask off the MSB and separate into trap type and cause.
> @@ -677,13 +678,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong deleg = async ? env->mideleg : env->medeleg;
> target_ulong tval = 0;
>
> - static const int ecall_cause_map[] = {
> - [PRV_U] = RISCV_EXCP_U_ECALL,
> - [PRV_S] = RISCV_EXCP_S_ECALL,
> - [PRV_H] = RISCV_EXCP_H_ECALL,
> - [PRV_M] = RISCV_EXCP_M_ECALL
> - };
> -
> if (!async) {
> /* set tval to badaddr for traps with address information */
> switch (cause) {
> @@ -704,7 +698,16 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> /* ecall is dispatched as one cause so translate based on mode */
> if (cause == RISCV_EXCP_U_ECALL) {
> assert(env->priv <= 3);
> - cause = ecall_cause_map[env->priv];
> +
> + if (env->priv == PRV_M) {
> + cause = RISCV_EXCP_M_ECALL;
> + } else if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
> + cause = RISCV_EXCP_VS_ECALL;
> + } else if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) {
> + cause = RISCV_EXCP_HS_ECALL;
> + } else if (env->priv == PRV_U) {
> + cause = RISCV_EXCP_U_ECALL;
> + }
> }
> }
>
> @@ -714,7 +717,42 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> if (env->priv <= PRV_S &&
> cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
> /* handle the trap in S-mode */
> - target_ulong s = *env->mstatus;
> + if (riscv_has_ext(env, RVH)) {
> + target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
> +
> + if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
> + !riscv_cpu_force_hs_excep_enabled(env)) {
> + /* Trap to VS mode */
> + } else if (riscv_cpu_virt_enabled(env)) {
> + /* Trap into HS mode, from virt */
> + riscv_cpu_swap_hypervisor_regs(env);
> + env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
> + get_field(env->hstatus, HSTATUS_SPV));
> + env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
> + get_field(*env->mstatus, SSTATUS_SPP));
> + env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> + riscv_cpu_virt_enabled(env));
> +
> + if (riscv_cpu_force_hs_excep_enabled(env)) {
> + env->hstatus = set_field(env->hstatus, HSTATUS_STL, 1);
> + } else {
> + env->hstatus = set_field(env->hstatus, HSTATUS_STL, 0);
> + }
> +
> + riscv_cpu_set_virt_enabled(env, VIRT_OFF);
> + riscv_cpu_set_force_hs_excep(env, CLEAR_HS_EXCEP);
> + } else {
> + /* Trap into HS mode */
> + env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
> + get_field(env->hstatus, HSTATUS_SPV));
> + env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
> + get_field(*env->mstatus, SSTATUS_SPP));
> + env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
> + riscv_cpu_virt_enabled(env));
> + }
> + }
> +
> + s = *env->mstatus;
> s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
> get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
> s = set_field(s, MSTATUS_SPP, env->priv);
> @@ -728,7 +766,20 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> riscv_cpu_set_mode(env, PRV_S);
> } else {
> /* handle the trap in M-mode */
> - target_ulong s = *env->mstatus;
> + if (riscv_has_ext(env, RVH)) {
> + if (riscv_cpu_virt_enabled(env)) {
> + riscv_cpu_swap_hypervisor_regs(env);
> + }
> + *env->mstatus = set_field(*env->mstatus, MSTATUS_MPV,
> + riscv_cpu_virt_enabled(env));
> + *env->mstatus = set_field(*env->mstatus, MSTATUS_MTL,
> + riscv_cpu_force_hs_excep_enabled(env));
> +
> + /* Trapping to M mode, virt is disabled */
> + riscv_cpu_set_virt_enabled(env, VIRT_OFF);
> + }
> +
> + s = *env->mstatus;
> s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
> get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
> s = set_field(s, MSTATUS_MPP, env->priv);
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 30ec8c0a8e..47be4b1d42 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -255,8 +255,8 @@ static const target_ulong delegable_excps =
> (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
> (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
> (1ULL << (RISCV_EXCP_U_ECALL)) |
> - (1ULL << (RISCV_EXCP_S_ECALL)) |
> - (1ULL << (RISCV_EXCP_H_ECALL)) |
> + (1ULL << (RISCV_EXCP_VS_ECALL)) |
> + (1ULL << (RISCV_EXCP_HS_ECALL)) |
> (1ULL << (RISCV_EXCP_M_ECALL)) |
> (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
> (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
next prev parent reply other threads:[~2019-09-20 14:03 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 23:37 [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension Alistair Francis
2019-08-27 15:26 ` Chih-Min Chao
2019-09-10 13:43 ` Palmer Dabbelt
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode Alistair Francis
2019-08-27 15:44 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-08-28 0:08 ` Alistair Francis
2019-09-10 13:44 ` [Qemu-devel] " Palmer Dabbelt
2019-09-16 15:57 ` Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode Alistair Francis
2019-08-27 15:46 ` Chih-Min Chao
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-10-16 20:56 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-08-27 15:50 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-09-11 8:24 ` Palmer Dabbelt
2019-09-11 14:54 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-09-17 23:33 ` Alistair Francis
2019-09-18 1:59 ` Jonathan Behrens
2019-09-18 23:47 ` Alistair Francis
2019-09-19 14:50 ` Richard Henderson
2019-09-19 16:58 ` Jonathan Behrens
2019-10-25 20:28 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Alistair Francis
2019-09-11 14:17 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-09-14 20:30 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-09-14 20:30 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-09-14 20:30 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-09-14 20:32 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support Alistair Francis
2019-09-20 14:01 ` Palmer Dabbelt [this message]
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-01 18:33 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-02 23:52 ` Palmer Dabbelt
2019-10-16 21:01 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-03 15:53 ` Palmer Dabbelt
2019-10-07 18:05 ` Alistair Francis
2019-10-16 19:02 ` Palmer Dabbelt
2019-10-16 21:25 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU Alistair Francis
2019-10-07 16:15 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-10-08 17:54 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-16 21:14 ` Alistair Francis
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-10-08 18:53 ` Palmer Dabbelt
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