From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-riscv@nongnu.org, Anup Patel <Anup.Patel@wdc.com>,
qemu-devel@nongnu.org, Atish Patra <Atish.Patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
alistair23@gmail.com
Subject: Re: [PATCH v1 24/28] target/riscv: Implement second stage MMU
Date: Mon, 07 Oct 2019 09:15:59 -0700 (PDT) [thread overview]
Message-ID: <mhng-a9412752-518e-4527-ad6c-3830ddead66d@palmer-si-x1c4> (raw)
In-Reply-To: <67e93a4f45693067abb03441e159b1f4a0a48276.1566603412.git.alistair.francis@wdc.com>
On Fri, 23 Aug 2019 16:38:52 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_helper.c | 96 +++++++++++++++++++++++++++++++++++----
> 1 file changed, 86 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 8b9871f9ea..188d5cb39f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -337,13 +337,40 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> * (riscv_cpu_do_interrupt) is correct */
>
> int mode = mmu_idx;
> + bool use_background = false;
>
> + /*
> + * Check if we should use the background registers for the two
> + * stage translation. We don't need to check if we actually need
> + * two stage translation as that happened before this function
> + * was called. Background registers will be used if the guest has
> + * forced a two stage translation to be on (in HS or M mode).
> + */
> if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> if (get_field(*env->mstatus, MSTATUS_MPRV)) {
> mode = get_field(*env->mstatus, MSTATUS_MPP);
> +
> + if (riscv_has_ext(env, RVH) &&
> + get_field(*env->mstatus, MSTATUS_MPV)) {
> + use_background = true;
> + }
> }
> }
>
> + if (mode == PRV_S && access_type != MMU_INST_FETCH &&
> + riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
> + if (get_field(env->hstatus, HSTATUS_SPRV)) {
> + mode = get_field(*env->mstatus, SSTATUS_SPP);
> + use_background = true;
> + }
> + }
> +
> + if (first_stage == false) {
> + /* We are in stage 2 translation, this is similar to stage 1. */
> + /* Stage 2 is always taken as U-mode */
> + mode = PRV_U;
> + }
> +
> if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
> *physical = addr;
> *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> @@ -353,13 +380,30 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> *prot = 0;
>
> target_ulong base;
> - int levels, ptidxbits, ptesize, vm, sum;
> - int mxr = get_field(*env->mstatus, MSTATUS_MXR);
> + int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
> +
> + if (first_stage == true) {
> + mxr = get_field(*env->mstatus, MSTATUS_MXR);
> + } else {
> + mxr = get_field(env->vsstatus, MSTATUS_MXR);
> + }
>
> if (env->priv_ver >= PRIV_VERSION_1_10_0) {
> - base = get_field(env->satp, SATP_PPN) << PGSHIFT;
> + if (first_stage == true) {
> + if (use_background) {
> + base = get_field(env->vsatp, SATP_PPN) << PGSHIFT;
> + vm = get_field(env->vsatp, SATP_MODE);
> + } else {
> + base = get_field(env->satp, SATP_PPN) << PGSHIFT;
> + vm = get_field(env->satp, SATP_MODE);
> + }
> + widened = 0;
> + } else {
> + base = get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
> + vm = get_field(env->hgatp, HGATP_MODE);
> + widened = 2;
> + }
> sum = get_field(*env->mstatus, MSTATUS_SUM);
> - vm = get_field(env->satp, SATP_MODE);
> switch (vm) {
> case VM_1_10_SV32:
> levels = 2; ptidxbits = 10; ptesize = 4; break;
> @@ -377,6 +421,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> g_assert_not_reached();
> }
> } else {
> + widened = 0;
> base = env->sptbr << PGSHIFT;
> sum = !get_field(*env->mstatus, MSTATUS_PUM);
> vm = get_field(*env->mstatus, MSTATUS_VM);
> @@ -397,9 +442,16 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> }
>
> CPUState *cs = env_cpu(env);
> - int va_bits = PGSHIFT + levels * ptidxbits;
> - target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> - target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask;
> + int va_bits = PGSHIFT + levels * ptidxbits + widened;
> + target_ulong mask, masked_msbs;
> +
> + if (TARGET_LONG_BITS > (va_bits - 1)) {
> + mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> + } else {
> + mask = 0;
> + }
> + masked_msbs = (addr >> (va_bits - 1)) & mask;
> +
> if (masked_msbs != 0 && masked_msbs != mask) {
> return TRANSLATE_FAIL;
> }
> @@ -411,17 +463,36 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> restart:
> #endif
> for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
> - target_ulong idx = (addr >> (PGSHIFT + ptshift)) &
> + target_ulong idx;
> + if (i == 0) {
> + idx = (addr >> (PGSHIFT + ptshift)) &
> + ((1 << (ptidxbits + widened)) - 1);
> + } else {
> + idx = (addr >> (PGSHIFT + ptshift)) &
> ((1 << ptidxbits) - 1);
> + }
>
> /* check that physical address of PTE is legal */
> - target_ulong pte_addr = base + idx * ptesize;
> + target_ulong pte_addr;
> +
> + if (two_stage && first_stage) {
> + hwaddr vbase;
> +
> + /* Do the second stage translation on the base PTE address. */
> + get_physical_address(env, &vbase, prot, base, access_type,
> + mmu_idx, false, true);
> +
> + pte_addr = vbase + idx * ptesize;
> + } else {
> + pte_addr = base + idx * ptesize;
> + }
>
> if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> 1 << MMU_DATA_LOAD, PRV_S)) {
> return TRANSLATE_PMP_FAIL;
> }
> +
> #if defined(TARGET_RISCV32)
> target_ulong pte = ldl_phys(cs->as, pte_addr);
> #elif defined(TARGET_RISCV64)
> @@ -507,7 +578,12 @@ restart:
> /* for superpage mappings, make a fake leaf PTE for the TLB's
> benefit. */
> target_ulong vpn = addr >> PGSHIFT;
> - *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
> + if (i == 0) {
> + *physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) <<
> + PGSHIFT;
> + } else {
> + *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
> + }
>
> /* set permissions on the TLB entry */
> if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
next prev parent reply other threads:[~2019-10-07 16:25 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 23:37 [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension Alistair Francis
2019-08-27 15:26 ` Chih-Min Chao
2019-09-10 13:43 ` Palmer Dabbelt
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode Alistair Francis
2019-08-27 15:44 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-08-28 0:08 ` Alistair Francis
2019-09-10 13:44 ` [Qemu-devel] " Palmer Dabbelt
2019-09-16 15:57 ` Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode Alistair Francis
2019-08-27 15:46 ` Chih-Min Chao
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-10-16 20:56 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-08-27 15:50 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-09-11 8:24 ` Palmer Dabbelt
2019-09-11 14:54 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-09-17 23:33 ` Alistair Francis
2019-09-18 1:59 ` Jonathan Behrens
2019-09-18 23:47 ` Alistair Francis
2019-09-19 14:50 ` Richard Henderson
2019-09-19 16:58 ` Jonathan Behrens
2019-10-25 20:28 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Alistair Francis
2019-09-11 14:17 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-09-14 20:30 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-09-14 20:30 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-09-14 20:30 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-09-14 20:32 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support Alistair Francis
2019-09-20 14:01 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-01 18:33 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-02 23:52 ` Palmer Dabbelt
2019-10-16 21:01 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-03 15:53 ` Palmer Dabbelt
2019-10-07 18:05 ` Alistair Francis
2019-10-16 19:02 ` Palmer Dabbelt
2019-10-16 21:25 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU Alistair Francis
2019-10-07 16:15 ` Palmer Dabbelt [this message]
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-10-08 17:54 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-16 21:14 ` Alistair Francis
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-10-08 18:53 ` Palmer Dabbelt
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