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From: Icenowy Zheng <uwu@icenowy.me>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
	Simon Glass <sjg@chromium.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Green Wan <green.wan@sifive.com>,
	u-boot@lists.denx.de
Subject: Re: [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability
Date: Thu, 13 Jul 2023 02:59:10 +0800	[thread overview]
Message-ID: <092f214715ac5888a3afa8701a43aae021687cfa.camel@icenowy.me> (raw)
In-Reply-To: <alpine.DEB.2.21.2307111643110.57020@angie.orcam.me.uk>

在 2023-07-12星期三的 14:13 +0100，Maciej W. Rozycki写道：
> On Wed, 28 Jun 2023, Icenowy Zheng wrote:
> 
> > When building the package `rustc` for AOSC OS on HiFive Unmatched,
> > random SIGSEGV prevents the package from getting correctly built.
> > Downclocking the CPU PLL clock seems to allow rustc to be built,
> > although taking much more time.
> > 
> > Downclock the CPU PLL frequency for stability.
> 
>  FYI, I've been observing occasional (less than 1 bit per 10GiB of
> data 
> moved) single-bit data corruption on DRAM writes with my HiFive
> Unmatched, 
> but your change does not appear to make any difference with my
> system.
> 
>  FWIW, given the price and amount of DRAM used I think it makes no
> sense 
> to build computers equipped with a DRAM subsystem without ECC
> nowadays.

Well the HiFive Unmatched board looks like it has a DRAM chip for ECC,
but whether this is activated is not known...

> 
>   Maciej


  reply	other threads:[~2023-07-12 18:59 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-28  8:15 [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability Icenowy Zheng
2023-07-12 13:13 ` Maciej W. Rozycki
2023-07-12 18:59   ` Icenowy Zheng [this message]
2023-07-12 20:09     ` Maciej W. Rozycki

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