From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Icenowy Zheng <uwu@icenowy.me>
Cc: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
Simon Glass <sjg@chromium.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Green Wan <green.wan@sifive.com>,
u-boot@lists.denx.de
Subject: Re: [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability
Date: Wed, 12 Jul 2023 21:09:48 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2307122053200.57020@angie.orcam.me.uk> (raw)
In-Reply-To: <092f214715ac5888a3afa8701a43aae021687cfa.camel@icenowy.me>
On Thu, 13 Jul 2023, Icenowy Zheng wrote:
> > FWIW, given the price and amount of DRAM used I think it makes no
> > sense
> > to build computers equipped with a DRAM subsystem without ECC
> > nowadays.
>
> Well the HiFive Unmatched board looks like it has a DRAM chip for ECC,
> but whether this is activated is not known...
I don't think so. According to documentation and visual inspection of
the board it has eight 2Gx8 DRAM chips. For ECC it would have to have
nine 2Gx8 chips.
Maciej
prev parent reply other threads:[~2023-07-12 20:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-28 8:15 [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability Icenowy Zheng
2023-07-12 13:13 ` Maciej W. Rozycki
2023-07-12 18:59 ` Icenowy Zheng
2023-07-12 20:09 ` Maciej W. Rozycki [this message]
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