From: Icenowy Zheng <uwu@icenowy.me>
To: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
Simon Glass <sjg@chromium.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Green Wan <green.wan@sifive.com>
Cc: u-boot@lists.denx.de, Icenowy Zheng <uwu@icenowy.me>
Subject: [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability
Date: Wed, 28 Jun 2023 16:15:30 +0800 [thread overview]
Message-ID: <20230628081530.3184607-1-uwu@icenowy.me> (raw)
When building the package `rustc` for AOSC OS on HiFive Unmatched,
random SIGSEGV prevents the package from getting correctly built.
Downclocking the CPU PLL clock seems to allow rustc to be built,
although taking much more time.
Downclock the CPU PLL frequency for stability.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 706224b384..6b80cab588 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -8,7 +8,7 @@
/ {
cpus {
assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- assigned-clock-rates = <1200000000>;
+ assigned-clock-rates = <988000000>;
bootph-pre-ram;
cpu0: cpu@0 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
--
2.39.1
next reply other threads:[~2023-06-28 8:16 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-28 8:15 Icenowy Zheng [this message]
2023-07-12 13:13 ` [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability Maciej W. Rozycki
2023-07-12 18:59 ` Icenowy Zheng
2023-07-12 20:09 ` Maciej W. Rozycki
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