From: Pratyush Yadav <p.yadav@ti.com>
To: u-boot@lists.denx.de
Subject: [PATCH v9 18/28] mtd: spi-nor-core: Parse xSPI Profile 1.0 table
Date: Wed, 5 May 2021 15:11:28 +0530 [thread overview]
Message-ID: <20210505094138.30805-19-p.yadav@ti.com> (raw)
In-Reply-To: <20210505094138.30805-1-p.yadav@ti.com>
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
drivers/mtd/spi/spi-nor-core.c | 100 +++++++++++++++++++++++++++++++++
include/linux/mtd/spi-nor.h | 7 +++
2 files changed, 107 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 7704a62d62..f2327ebd4c 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -21,6 +21,7 @@
#include <linux/log2.h>
#include <linux/math64.h>
#include <linux/sizes.h>
+#include <linux/bitfield.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/spi-nor.h>
@@ -40,6 +41,8 @@
#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
+
struct sfdp_parameter_header {
u8 id_lsb;
u8 minor;
@@ -58,6 +61,7 @@ struct sfdp_parameter_header {
#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
+#define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
#define SFDP_SIGNATURE 0x50444653U
#define SFDP_JESD216_MAJOR 1
@@ -155,6 +159,16 @@ struct sfdp_header {
#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
+/* xSPI Profile 1.0 table (from JESD216D.01). */
+#define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
+#define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
+#define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
+#define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
+#define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
+#define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
+#define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
+#define PROFILE1_DUMMY_DEFAULT 20
+
struct sfdp_bfpt {
u32 dwords[BFPT_DWORD_MAX];
};
@@ -2095,6 +2109,86 @@ spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
return ret;
}
+/**
+ * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
+ * @nor: pointer to a 'struct spi_nor'
+ * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
+ * the 4-Byte Address Instruction Table length and version.
+ * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_parse_profile1(struct spi_nor *nor,
+ const struct sfdp_parameter_header *profile1_header,
+ struct spi_nor_flash_parameter *params)
+{
+ u32 *table, opcode, addr;
+ size_t len;
+ int ret, i;
+ u8 dummy;
+
+ len = profile1_header->length * sizeof(*table);
+ table = kmalloc(len, GFP_KERNEL);
+ if (!table)
+ return -ENOMEM;
+
+ addr = SFDP_PARAM_HEADER_PTP(profile1_header);
+ ret = spi_nor_read_sfdp(nor, addr, len, table);
+ if (ret)
+ goto out;
+
+ /* Fix endianness of the table DWORDs. */
+ for (i = 0; i < profile1_header->length; i++)
+ table[i] = le32_to_cpu(table[i]);
+
+ /* Get 8D-8D-8D fast read opcode and dummy cycles. */
+ opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
+
+ /*
+ * We don't know what speed the controller is running at. Find the
+ * dummy cycles for the fastest frequency the flash can run at to be
+ * sure we are never short of dummy cycles. A value of 0 means the
+ * frequency is not supported.
+ *
+ * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
+ * flashes set the correct value if needed in their fixup hooks.
+ */
+ dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]);
+ if (!dummy)
+ dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]);
+ if (!dummy)
+ dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]);
+ if (!dummy)
+ dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]);
+ if (!dummy)
+ dummy = PROFILE1_DUMMY_DEFAULT;
+
+ /* Round up to an even value to avoid tripping controllers up. */
+ dummy = ROUND_UP_TO(dummy, 2);
+
+ /* Update the fast read settings. */
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
+ 0, dummy, opcode,
+ SNOR_PROTO_8_8_8_DTR);
+
+ /*
+ * Set the Read Status Register dummy cycles and dummy address bytes.
+ */
+ if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY)
+ params->rdsr_dummy = 8;
+ else
+ params->rdsr_dummy = 4;
+
+ if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
+ params->rdsr_addr_nbytes = 4;
+ else
+ params->rdsr_addr_nbytes = 0;
+
+out:
+ kfree(table);
+ return ret;
+}
+
/**
* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
* @nor: pointer to a 'struct spi_nor'
@@ -2197,6 +2291,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
err = spi_nor_parse_microchip_sfdp(nor, param_header);
break;
+ case SFDP_PROFILE1_ID:
+ err = spi_nor_parse_profile1(nor, param_header, params);
+ break;
+
default:
break;
}
@@ -2925,6 +3023,8 @@ int spi_nor_scan(struct spi_nor *nor)
if (ret)
return ret;
+ nor->rdsr_dummy = params.rdsr_dummy;
+ nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
nor->name = mtd->name;
nor->size = mtd->size;
nor->erase_size = mtd->erasesize;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4394cb6e16..295583ed29 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -391,6 +391,8 @@ enum spi_nor_pp_command_index {
struct spi_nor_flash_parameter {
u64 size;
u32 page_size;
+ u8 rdsr_dummy;
+ u8 rdsr_addr_nbytes;
struct spi_nor_hwcaps hwcaps;
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
@@ -445,6 +447,9 @@ struct spi_flash {
* @read_opcode: the read opcode
* @read_dummy: the dummy needed by the read operation
* @program_opcode: the program opcode
+ * @rdsr_dummy dummy cycles needed for Read Status Register command.
+ * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
+ * command.
* @bank_read_cmd: Bank read cmd
* @bank_write_cmd: Bank write cmd
* @bank_curr: Current flash bank
@@ -486,6 +491,8 @@ struct spi_nor {
u8 read_opcode;
u8 read_dummy;
u8 program_opcode;
+ u8 rdsr_dummy;
+ u8 rdsr_addr_nbytes;
#ifdef CONFIG_SPI_FLASH_BAR
u8 bank_read_cmd;
u8 bank_write_cmd;
--
2.30.0
next prev parent reply other threads:[~2021-05-05 9:41 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 9:41 [PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 01/28] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 02/28] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 03/28] spi: spi-mem: export spi_mem_default_supports_op() Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 04/28] spi: spi-mem: add spi_mem_dtr_supports_op() Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 05/28] spi: cadence-qspi: Do not calibrate when device tree sets read delay Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 06/28] spi: cadence-qspi: Add a small delay before indirect writes Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 07/28] spi: cadence-qspi: Add support for octal DTR flashes Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 08/28] arm: mvebu: x530: Use tiny SPI NOR Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 09/28] mtd: spi-nor-core: Fix address width on flash chips > 16MB Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 10/28] mtd: spi-nor-core: Add a ->setup() hook Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 11/28] mtd: spi-nor-core: Move SFDP related declarations to top Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 12/28] mtd: spi-nor-core: Introduce flash-specific fixup hooks Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 13/28] mtd: spi-nor-core: Rework hwcaps selection Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 14/28] mtd: spi-nor-core: Do not set data direction when there is no data Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 15/28] mtd: spi-nor-core: Add support for DTR protocol Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 16/28] mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 17/28] mtd: spi-nor-core: Get command opcode extension type from BFPT Pratyush Yadav
2021-05-05 9:41 ` Pratyush Yadav [this message]
2021-05-05 9:41 ` [PATCH v9 19/28] mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 20/28] mtd: spi-nor-core: Enable octal DTR mode when possible Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 21/28] mtd: spi-nor-core: Do not make invalid quad enable fatal Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 22/28] mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 23/28] mtd: spi-nor-core: Perform a Soft Reset on shutdown Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 24/28] mtd: spi-nor-core: Perform a Soft Reset on boot Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 25/28] mtd: spi-nor-core: allow truncated erases Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 26/28] mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 27/28] mtd: spi-nor-core: Add support for Cypress Semper flash Pratyush Yadav
2021-05-05 9:41 ` [PATCH v9 28/28] mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode Pratyush Yadav
2021-05-10 13:20 ` [PATCH v9 00/28] mtd: spi-nor-core: add xSPI Octal DTR support Pratyush Yadav
2021-05-26 17:05 ` Jagan Teki
2021-05-27 16:23 ` Pratyush Yadav
2021-06-14 15:10 ` Pratyush Yadav
2021-06-23 12:02 ` Jagan Teki
2021-06-24 11:13 ` Pratyush Yadav
2021-06-25 15:32 ` Jagan Teki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210505094138.30805-19-p.yadav@ti.com \
--to=p.yadav@ti.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).