From: "Jan Beulich" <JBeulich@suse.com>
To: "xen-devel" <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Brian Woods <brian.woods@amd.com>, Wei Liu <wei.liu2@citrix.com>,
Roger Pau Monne <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH 3/5] x86/AMD: make C-state handling independent of Dom0
Date: Thu, 23 May 2019 06:18:11 -0600 [thread overview]
Message-ID: <5CE68F830200007800231B3B@prv1-mh.provo.novell.com> (raw)
Message-ID: <20190523121811.M2EsRaDEELiMFGH4nanCGsPUCB39OQ7TraxxsHWjsVg@z> (raw)
In-Reply-To: <5CE68CD30200007800231B01@prv1-mh.provo.novell.com>
At least for more recent CPUs, following what BKDG / PPR suggest for the
BIOS to surface via ACPI we can make ourselves independent of Dom0
uploading respective data.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
TBD: Can we set local_apic_timer_c2_ok to true? I can't seem to find any
statement in the BKDG / PPR as to whether the LAPIC timer continues
running in CC6.
TBD: We may want to verify that HLT indeed is configured to enter CC6.
TBD: Brian's series specifies .target_residency as 1000 for CC6; may
want to do so here as well. Question then is whether this value is
also suitable for the older families.
TBD: I guess we could extend this to families older then Fam15 as well.
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -110,6 +110,8 @@ boolean_param("lapic_timer_c2_ok", local
struct acpi_processor_power *__read_mostly processor_powers[NR_CPUS];
+static int8_t __read_mostly vendor_override;
+
struct hw_residencies
{
uint64_t mc0;
@@ -1211,6 +1213,9 @@ long set_cx_pminfo(uint32_t acpi_id, str
if ( pm_idle_save && pm_idle != acpi_processor_idle )
return 0;
+ if ( vendor_override > 0 )
+ return 0;
+
print_cx_pminfo(acpi_id, power);
cpu_id = get_cpu_id(acpi_id);
@@ -1283,6 +1288,98 @@ long set_cx_pminfo(uint32_t acpi_id, str
return 0;
}
+static void amd_cpuidle_init(struct acpi_processor_power *power)
+{
+ unsigned int i, nr = 0;
+ const struct cpuinfo_x86 *c = ¤t_cpu_data;
+ const unsigned int ecx_req = CPUID5_ECX_EXTENSIONS_SUPPORTED |
+ CPUID5_ECX_INTERRUPT_BREAK;
+ const struct acpi_processor_cx *cx = NULL;
+ static const struct acpi_processor_cx fam17[] = {
+ {
+ .type = ACPI_STATE_C1,
+ .entry_method = ACPI_CSTATE_EM_FFH,
+ .address = 0,
+ .latency = 1,
+ },
+ {
+ .type = ACPI_STATE_C2,
+ .entry_method = ACPI_CSTATE_EM_HALT,
+ .latency = 400,
+ },
+ };
+
+ if ( pm_idle_save && pm_idle != acpi_processor_idle )
+ return;
+
+ if ( vendor_override < 0 )
+ return;
+
+ switch ( c->x86 )
+ {
+ case 0x17:
+ if ( cpu_has_monitor && c->cpuid_level >= CPUID_MWAIT_LEAF &&
+ (cpuid_ecx(CPUID_MWAIT_LEAF) & ecx_req) == ecx_req )
+ {
+ cx = fam17;
+ nr = ARRAY_SIZE(fam17);
+ break;
+ }
+ /* fall through */
+ case 0x15:
+ case 0x16:
+ cx = &fam17[1];
+ nr = ARRAY_SIZE(fam17) - 1;
+ break;
+
+ default:
+ vendor_override = -1;
+ return;
+ }
+
+ power->flags.has_cst = true;
+
+ for ( i = 0; i < nr; ++i )
+ {
+ if ( cx[i].type > max_cstate )
+ break;
+ power->states[i + 1] = cx[i];
+ power->states[i + 1].idx = i + 1;
+ power->states[i + 1].target_residency = cx[i].latency * latency_factor;
+ }
+
+ if ( i )
+ {
+ power->count = i + 1;
+ power->safe_state = &power->states[i];
+
+ if ( !vendor_override )
+ {
+ if ( !boot_cpu_has(X86_FEATURE_ARAT) )
+ hpet_broadcast_init();
+
+ if ( !lapic_timer_init() )
+ {
+ vendor_override = -1;
+ cpuidle_init_cpu(power->cpu);
+ return;
+ }
+
+ if ( !pm_idle_save )
+ {
+ pm_idle_save = pm_idle;
+ pm_idle = acpi_processor_idle;
+ }
+
+ dead_idle = acpi_dead_idle;
+
+ vendor_override = 1;
+ }
+ }
+ else
+ vendor_override = -1;
+}
+
uint32_t pmstat_get_cx_nr(uint32_t cpuid)
{
return processor_powers[cpuid] ? processor_powers[cpuid]->count : 0;
@@ -1429,8 +1526,8 @@ static int cpu_callback(
int rc = 0;
/*
- * Only hook on CPU_UP_PREPARE because a dead cpu may utilize the info
- * to enter deep C-state.
+ * Only hook on CPU_UP_PREPARE / CPU_ONLINE because a dead cpu may utilize
+ * the info to enter deep C-state.
*/
switch ( action )
{
@@ -1439,6 +1536,12 @@ static int cpu_callback(
if ( !rc && cpuidle_current_governor->enable )
rc = cpuidle_current_governor->enable(processor_powers[cpu]);
break;
+
+ case CPU_ONLINE:
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+ processor_powers[cpu] )
+ amd_cpuidle_init(processor_powers[cpu]);
+ break;
}
return !rc ? NOTIFY_DONE : notifier_from_errno(rc);
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next prev parent reply other threads:[~2019-05-23 12:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-23 12:06 [PATCH 0/5] x86: CPU idle management adjustments Jan Beulich
2019-05-23 12:06 ` [Xen-devel] " Jan Beulich
2019-05-23 12:16 ` [PATCH 1/5] x86/cpuidle: switch to uniform meaning of "max_cstate=" Jan Beulich
2019-05-23 12:16 ` [Xen-devel] " Jan Beulich
2019-06-10 15:48 ` Andrew Cooper
2019-06-11 12:13 ` Jan Beulich
2019-05-23 12:17 ` [PATCH 2/5] x86/cpuidle: really use C1 for "urgent" CPUs Jan Beulich
2019-05-23 12:17 ` [Xen-devel] " Jan Beulich
2019-06-10 15:50 ` Andrew Cooper
2019-05-23 12:18 ` Jan Beulich [this message]
2019-05-23 12:18 ` [Xen-devel] [PATCH 3/5] x86/AMD: make C-state handling independent of Dom0 Jan Beulich
2019-06-10 16:28 ` Andrew Cooper
2019-06-11 12:42 ` Jan Beulich
2019-06-18 17:22 ` Woods, Brian
2019-06-19 6:20 ` Jan Beulich
2019-06-19 15:54 ` Woods, Brian
2019-06-21 6:37 ` Jan Beulich
2019-06-21 14:29 ` Woods, Brian
2019-06-21 14:56 ` Jan Beulich
2019-06-21 15:26 ` Woods, Brian
2019-05-23 12:18 ` [PATCH 4/5] x86: allow limiting the max C-state sub-state Jan Beulich
2019-05-23 12:18 ` [Xen-devel] " Jan Beulich
2019-06-10 16:43 ` Andrew Cooper
2019-06-11 12:46 ` Jan Beulich
2019-05-23 12:19 ` [PATCH 5/5] tools/libxc: allow controlling " Jan Beulich
2019-05-23 12:19 ` [Xen-devel] " Jan Beulich
2019-05-24 14:00 ` Wei Liu
2019-05-24 14:00 ` [Xen-devel] " Wei Liu
2019-06-10 16:54 ` Andrew Cooper
2019-06-11 12:50 ` Jan Beulich
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