From: "Shankar, Uma" <uma.shankar@intel.com> To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Cc: "Kulkarni, Vandita" <vandita.kulkarni@intel.com>, "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>, "Sharma, Swati2" <swati2.sharma@intel.com> Subject: RE: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Date: Sun, 18 Oct 2020 21:41:21 +0000 [thread overview] Message-ID: <0bc6df6f31934c4e99777e78a994808c@intel.com> (raw) In-Reply-To: <20201015105259.27934-5-ankit.k.nautiyal@intel.com> > -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Thursday, October 15, 2020 4:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; > Sharma, Swati2 <swati2.sharma@intel.com> > Subject: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure > > HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the > sink. > > This patch captures these in dfp cap structure in intel_dp and uses these to > prune connector modes that cannot be supported by the PCON and sink FRL > bandwidth. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++-- > 2 files changed, 32 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 0b5df8e44966..e2f58d0575a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1398,6 +1398,7 @@ struct intel_dp { > struct { > int min_tmds_clock, max_tmds_clock; > int max_dotclock; > + int pcon_max_frl, sink_max_frl; Append it with bw or rate. > u8 max_bpc; > bool ycbcr_444_to_420; > } dfp; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 0902a9aeeda1..cd6934f28f32 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct > intel_connector *connector, > const struct drm_display_info *info = &connector->base.display_info; > int tmds_clock; > > + /* If PCON and HDMI2.1 sink both support FRL MODE, check FRL Use multi line comment style. > + * bandwidth constraints. > + */ > + if (intel_dp->dfp.pcon_max_frl) { > + int target_bw; > + int max_frl_bw; > + int bpp = intel_dp_mode_min_output_bpp(&connector->base, > mode); > + > + target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000); To avoid any roundup errors, it would be good to multiple max_frl_bw by 1000000 than dividing target_clock > + > + max_frl_bw = min(intel_dp->dfp.pcon_max_frl, > + intel_dp->dfp.sink_max_frl); > + if (target_bw > max_frl_bw) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > + } > + > if (intel_dp->dfp.max_dotclock && > target_clock > intel_dp->dfp.max_dotclock) > return MODE_CLOCK_HIGH; > @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, > intel_dp->downstream_ports, > edid); > > + intel_dp->dfp.pcon_max_frl = > + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, > + intel_dp->downstream_ports); > + > + intel_dp->dfp.sink_max_frl = > +drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux); > + > drm_dbg_kms(&i915->drm, > - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, > TMDS clock %d-%d\n", > + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, > TMDS clock > +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n", > connector->base.base.id, connector->base.name, > intel_dp->dfp.max_bpc, > intel_dp->dfp.max_dotclock, > intel_dp->dfp.min_tmds_clock, > - intel_dp->dfp.max_tmds_clock); > + intel_dp->dfp.max_tmds_clock, > + intel_dp->dfp.pcon_max_frl, > + intel_dp->dfp.sink_max_frl); > } > > static void > @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > intel_dp->dfp.min_tmds_clock = 0; > intel_dp->dfp.max_tmds_clock = 0; > > + intel_dp->dfp.pcon_max_frl = 0; > + intel_dp->dfp.sink_max_frl = 0; > + > intel_dp->dfp.ycbcr_444_to_420 = false; > connector->base.ycbcr_420_allowed = false; } > -- > 2.17.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: "Shankar, Uma" <uma.shankar@intel.com> To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>, "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org> Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org> Subject: Re: [Intel-gfx] [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Date: Sun, 18 Oct 2020 21:41:21 +0000 [thread overview] Message-ID: <0bc6df6f31934c4e99777e78a994808c@intel.com> (raw) In-Reply-To: <20201015105259.27934-5-ankit.k.nautiyal@intel.com> > -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Thursday, October 15, 2020 4:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; > Sharma, Swati2 <swati2.sharma@intel.com> > Subject: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure > > HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the > sink. > > This patch captures these in dfp cap structure in intel_dp and uses these to > prune connector modes that cannot be supported by the PCON and sink FRL > bandwidth. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++-- > 2 files changed, 32 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 0b5df8e44966..e2f58d0575a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1398,6 +1398,7 @@ struct intel_dp { > struct { > int min_tmds_clock, max_tmds_clock; > int max_dotclock; > + int pcon_max_frl, sink_max_frl; Append it with bw or rate. > u8 max_bpc; > bool ycbcr_444_to_420; > } dfp; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 0902a9aeeda1..cd6934f28f32 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct > intel_connector *connector, > const struct drm_display_info *info = &connector->base.display_info; > int tmds_clock; > > + /* If PCON and HDMI2.1 sink both support FRL MODE, check FRL Use multi line comment style. > + * bandwidth constraints. > + */ > + if (intel_dp->dfp.pcon_max_frl) { > + int target_bw; > + int max_frl_bw; > + int bpp = intel_dp_mode_min_output_bpp(&connector->base, > mode); > + > + target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000); To avoid any roundup errors, it would be good to multiple max_frl_bw by 1000000 than dividing target_clock > + > + max_frl_bw = min(intel_dp->dfp.pcon_max_frl, > + intel_dp->dfp.sink_max_frl); > + if (target_bw > max_frl_bw) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > + } > + > if (intel_dp->dfp.max_dotclock && > target_clock > intel_dp->dfp.max_dotclock) > return MODE_CLOCK_HIGH; > @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, > intel_dp->downstream_ports, > edid); > > + intel_dp->dfp.pcon_max_frl = > + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, > + intel_dp->downstream_ports); > + > + intel_dp->dfp.sink_max_frl = > +drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux); > + > drm_dbg_kms(&i915->drm, > - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, > TMDS clock %d-%d\n", > + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, > TMDS clock > +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n", > connector->base.base.id, connector->base.name, > intel_dp->dfp.max_bpc, > intel_dp->dfp.max_dotclock, > intel_dp->dfp.min_tmds_clock, > - intel_dp->dfp.max_tmds_clock); > + intel_dp->dfp.max_tmds_clock, > + intel_dp->dfp.pcon_max_frl, > + intel_dp->dfp.sink_max_frl); > } > > static void > @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > intel_dp->dfp.min_tmds_clock = 0; > intel_dp->dfp.max_tmds_clock = 0; > > + intel_dp->dfp.pcon_max_frl = 0; > + intel_dp->dfp.sink_max_frl = 0; > + > intel_dp->dfp.ycbcr_444_to_420 = false; > connector->base.ycbcr_420_allowed = false; } > -- > 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-18 21:41 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-15 10:52 [RFC 00/13] Add support for DP-HDMI2.1 PCON Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-15 10:52 ` [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 20:47 ` Shankar, Uma 2020-10-18 20:47 ` [Intel-gfx] " Shankar, Uma 2020-11-01 5:31 ` Nautiyal, Ankit K 2020-11-01 5:31 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 20:47 ` Shankar, Uma 2020-10-18 20:47 ` [Intel-gfx] " Shankar, Uma 2020-11-01 5:41 ` Nautiyal, Ankit K 2020-11-01 5:41 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 21:33 ` Shankar, Uma 2020-10-18 21:33 ` [Intel-gfx] " Shankar, Uma 2020-11-01 5:53 ` Nautiyal, Ankit K 2020-11-01 5:53 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 21:41 ` Shankar, Uma [this message] 2020-10-18 21:41 ` Shankar, Uma 2020-11-01 5:56 ` Nautiyal, Ankit K 2020-11-01 5:56 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 22:14 ` Shankar, Uma 2020-10-18 22:14 ` [Intel-gfx] " Shankar, Uma 2020-11-01 6:01 ` Nautiyal, Ankit K 2020-11-01 6:01 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 06/13] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 22:21 ` Shankar, Uma 2020-10-18 22:21 ` [Intel-gfx] " Shankar, Uma 2020-11-01 6:06 ` Nautiyal, Ankit K 2020-11-01 6:06 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 07/13] drm/dp_helper: Add support for link status and link recovery Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 22:37 ` Shankar, Uma 2020-10-18 22:37 ` [Intel-gfx] " Shankar, Uma 2020-11-01 6:18 ` Nautiyal, Ankit K 2020-11-01 6:18 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 08/13] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 22:49 ` Shankar, Uma 2020-10-18 22:49 ` [Intel-gfx] " Shankar, Uma 2020-11-01 6:26 ` Nautiyal, Ankit K 2020-11-01 6:26 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 23:01 ` Shankar, Uma 2020-10-18 23:01 ` [Intel-gfx] " Shankar, Uma 2020-11-01 6:52 ` Nautiyal, Ankit K 2020-11-01 6:52 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-18 23:19 ` Shankar, Uma 2020-10-18 23:19 ` [Intel-gfx] " Shankar, Uma 2020-11-01 7:00 ` Nautiyal, Ankit K 2020-11-01 7:00 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-15 14:19 ` kernel test robot 2020-10-15 14:19 ` [RFC PATCH] drm/i915: intel_dp_get_pcon_dsc_cap() can be static kernel test robot 2020-10-15 14:47 ` [Intel-gfx] [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder kernel test robot 2020-10-15 15:10 ` kernel test robot 2020-10-15 17:07 ` kernel test robot 2020-10-15 17:07 ` [PATCH] drm/i915: fix semicolon.cocci warnings kernel test robot 2020-10-18 23:32 ` [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Shankar, Uma 2020-10-18 23:32 ` [Intel-gfx] " Shankar, Uma 2020-10-18 23:34 ` Shankar, Uma 2020-10-18 23:34 ` [Intel-gfx] " Shankar, Uma 2020-11-01 7:14 ` Nautiyal, Ankit K 2020-11-01 7:14 ` [Intel-gfx] " Nautiyal, Ankit K 2020-11-01 7:13 ` Nautiyal, Ankit K 2020-11-01 7:13 ` [Intel-gfx] " Nautiyal, Ankit K 2020-10-15 10:52 ` [RFC 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-15 10:52 ` [RFC 13/13] drm/i915: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal 2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal 2020-10-15 11:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev3) Patchwork 2020-10-15 11:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2020-10-15 12:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-10-15 13:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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