From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: vandita.kulkarni@intel.com, uma.shankar@intel.com,
dri-devel@lists.freedesktop.org, swati2.sharma@intel.com
Subject: [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1
Date: Thu, 15 Oct 2020 16:22:47 +0530 [thread overview]
Message-ID: <20201015105259.27934-2-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20201015105259.27934-1-ankit.k.nautiyal@intel.com>
From: Swati Sharma <swati2.sharma@intel.com>
The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific
Data block) to have fields related to newly defined methods of FRL
(Fixed Rate Link) levels, number of lanes supported, DSC Color bit
depth, VRR min/max, FVA (Fast Vactive), ALLM etc.
This patch adds the new HFVSDB fields that are required for
HDMI2.1.
Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b27a0e2169c8..1cc5c2c73282 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -229,6 +229,36 @@ struct detailed_timing {
DRM_EDID_YCBCR420_DC_36 | \
DRM_EDID_YCBCR420_DC_30)
+/* HDMI 2.1 additional fields */
+#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
+#define DRM_EDID_FAPA_START_LOCATION (1 << 0)
+#define DRM_EDID_ALLM (1 << 1)
+#define DRM_EDID_FVA (1 << 2)
+
+/* Deep Color specific */
+#define DRM_EDID_DC_30BIT_420 (1 << 0)
+#define DRM_EDID_DC_36BIT_420 (1 << 1)
+#define DRM_EDID_DC_48BIT_420 (1 << 2)
+
+/* VRR specific */
+#define DRM_EDID_CNMVRR (1 << 3)
+#define DRM_EDID_CINEMA_VRR (1 << 4)
+#define DRM_EDID_MDELTA (1 << 5)
+#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
+#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
+#define DRM_EDID_VRR_MIN_MASK 0x3f
+
+/* DSC specific */
+#define DRM_EDID_DSC_10BPC (1 << 0)
+#define DRM_EDID_DSC_12BPC (1 << 1)
+#define DRM_EDID_DSC_16BPC (1 << 2)
+#define DRM_EDID_DSC_ALL_BPP (1 << 3)
+#define DRM_EDID_DSC_NATIVE_420 (1 << 6)
+#define DRM_EDID_DSC_1P2 (1 << 7)
+#define DRM_EDID_DSC_MAX_FRL_RATE 0xf
+#define DRM_EDID_DSC_MAX_SLICES 0xf
+#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
+
/* ELD Header Block */
#define DRM_ELD_HEADER_BLOCK_SIZE 4
--
2.17.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1
Date: Thu, 15 Oct 2020 16:22:47 +0530 [thread overview]
Message-ID: <20201015105259.27934-2-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20201015105259.27934-1-ankit.k.nautiyal@intel.com>
From: Swati Sharma <swati2.sharma@intel.com>
The HDMI2.1 extends HFVSBD (HDMI Forum Vendor Specific
Data block) to have fields related to newly defined methods of FRL
(Fixed Rate Link) levels, number of lanes supported, DSC Color bit
depth, VRR min/max, FVA (Fast Vactive), ALLM etc.
This patch adds the new HFVSDB fields that are required for
HDMI2.1.
Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b27a0e2169c8..1cc5c2c73282 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -229,6 +229,36 @@ struct detailed_timing {
DRM_EDID_YCBCR420_DC_36 | \
DRM_EDID_YCBCR420_DC_30)
+/* HDMI 2.1 additional fields */
+#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
+#define DRM_EDID_FAPA_START_LOCATION (1 << 0)
+#define DRM_EDID_ALLM (1 << 1)
+#define DRM_EDID_FVA (1 << 2)
+
+/* Deep Color specific */
+#define DRM_EDID_DC_30BIT_420 (1 << 0)
+#define DRM_EDID_DC_36BIT_420 (1 << 1)
+#define DRM_EDID_DC_48BIT_420 (1 << 2)
+
+/* VRR specific */
+#define DRM_EDID_CNMVRR (1 << 3)
+#define DRM_EDID_CINEMA_VRR (1 << 4)
+#define DRM_EDID_MDELTA (1 << 5)
+#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
+#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
+#define DRM_EDID_VRR_MIN_MASK 0x3f
+
+/* DSC specific */
+#define DRM_EDID_DSC_10BPC (1 << 0)
+#define DRM_EDID_DSC_12BPC (1 << 1)
+#define DRM_EDID_DSC_16BPC (1 << 2)
+#define DRM_EDID_DSC_ALL_BPP (1 << 3)
+#define DRM_EDID_DSC_NATIVE_420 (1 << 6)
+#define DRM_EDID_DSC_1P2 (1 << 7)
+#define DRM_EDID_DSC_MAX_FRL_RATE 0xf
+#define DRM_EDID_DSC_MAX_SLICES 0xf
+#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
+
/* ELD Header Block */
#define DRM_ELD_HEADER_BLOCK_SIZE 4
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-15 11:00 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-15 10:52 [RFC 00/13] Add support for DP-HDMI2.1 PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 10:52 ` Ankit Nautiyal [this message]
2020-10-15 10:52 ` [Intel-gfx] [RFC 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 Ankit Nautiyal
2020-10-18 20:47 ` Shankar, Uma
2020-10-18 20:47 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:31 ` Nautiyal, Ankit K
2020-11-01 5:31 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 02/13] drm/edid: Parse MAX_FRL field from HFVSDB block Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 20:47 ` Shankar, Uma
2020-10-18 20:47 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:41 ` Nautiyal, Ankit K
2020-11-01 5:41 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 03/13] drm/dp_helper: Add FRL training support for a DP-HDMI2.1 PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 21:33 ` Shankar, Uma
2020-10-18 21:33 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:53 ` Nautiyal, Ankit K
2020-11-01 5:53 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 21:41 ` Shankar, Uma
2020-10-18 21:41 ` [Intel-gfx] " Shankar, Uma
2020-11-01 5:56 ` Nautiyal, Ankit K
2020-11-01 5:56 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 05/13] drm/i915: Add support for starting FRL training for HDMI2.1 via PCON Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:14 ` Shankar, Uma
2020-10-18 22:14 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:01 ` Nautiyal, Ankit K
2020-11-01 6:01 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 06/13] drm/i915: Check for FRL training before DP Link training Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:21 ` Shankar, Uma
2020-10-18 22:21 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:06 ` Nautiyal, Ankit K
2020-11-01 6:06 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 07/13] drm/dp_helper: Add support for link status and link recovery Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:37 ` Shankar, Uma
2020-10-18 22:37 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:18 ` Nautiyal, Ankit K
2020-11-01 6:18 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 08/13] drm/i915: Add support for enabling link status and recovery Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 22:49 ` Shankar, Uma
2020-10-18 22:49 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:26 ` Nautiyal, Ankit K
2020-11-01 6:26 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 09/13] drm/edid: Parse DSC1.2 cap fields from HFVSDB block Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 23:01 ` Shankar, Uma
2020-10-18 23:01 ` [Intel-gfx] " Shankar, Uma
2020-11-01 6:52 ` Nautiyal, Ankit K
2020-11-01 6:52 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 10/13] drm/dp_helper: Add support for Configuring DSC for HDMI2.1 Pcon Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-18 23:19 ` Shankar, Uma
2020-10-18 23:19 ` [Intel-gfx] " Shankar, Uma
2020-11-01 7:00 ` Nautiyal, Ankit K
2020-11-01 7:00 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 14:19 ` kernel test robot
2020-10-15 14:19 ` [RFC PATCH] drm/i915: intel_dp_get_pcon_dsc_cap() can be static kernel test robot
2020-10-15 14:47 ` [Intel-gfx] [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder kernel test robot
2020-10-15 15:10 ` kernel test robot
2020-10-15 17:07 ` kernel test robot
2020-10-15 17:07 ` [PATCH] drm/i915: fix semicolon.cocci warnings kernel test robot
2020-10-18 23:32 ` [RFC 11/13] drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder Shankar, Uma
2020-10-18 23:32 ` [Intel-gfx] " Shankar, Uma
2020-10-18 23:34 ` Shankar, Uma
2020-10-18 23:34 ` [Intel-gfx] " Shankar, Uma
2020-11-01 7:14 ` Nautiyal, Ankit K
2020-11-01 7:14 ` [Intel-gfx] " Nautiyal, Ankit K
2020-11-01 7:13 ` Nautiyal, Ankit K
2020-11-01 7:13 ` [Intel-gfx] " Nautiyal, Ankit K
2020-10-15 10:52 ` [RFC 12/13] drm/i915: Add helper functions for calculating DSC parameters for HDMI2.1 Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 10:52 ` [RFC 13/13] drm/i915: Configure PCON for DSC1.1 to DSC1.2 encoding Ankit Nautiyal
2020-10-15 10:52 ` [Intel-gfx] " Ankit Nautiyal
2020-10-15 11:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for DP-HDMI2.1 PCON (rev3) Patchwork
2020-10-15 11:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-15 12:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-15 13:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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