From: Joseph Lo <josephl@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock
Date: Tue, 11 Dec 2018 16:52:05 +0800 [thread overview]
Message-ID: <0f424403-50b7-983b-069b-1a7b757bf26a@nvidia.com> (raw)
In-Reply-To: <827e05c8-13b9-fb5e-7bca-1a34b81763b1@nvidia.com>
On 12/7/18 10:57 PM, Jon Hunter wrote:
>
> On 04/12/2018 09:25, Joseph Lo wrote:
>> Enable DFLL clock for Jetson TX1 platform.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> ---
>> .../boot/dts/nvidia/tegra210-p2371-2180.dts | 20 +++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> index 37e3c46e753f..53f497c2b3ff 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> @@ -78,4 +78,24 @@
>> };
>> };
>> };
>> +
>> + clock@70110000 {
>> + status = "okay";
>> + nvidia,pwm-to-pmic;
>> + nvidia,init-uv = <1000000>;
>> + nvidia,align-offset-uv = <708000>;
>> + nvidia,align-step-uv = <19200>;
>> + nvidia,sample-rate = <25000>;
>> + nvidia,droop-ctrl = <0x00000f00>;
>> + nvidia,force-mode = <1>;
>> + nvidia,cf = <6>;
>> + nvidia,ci = <0>;
>> + nvidia,cg = <2>;
>> + nvidia,idle-override;
>> + nvidia,one-shot-calibrate;
>
> I don't see any Documentation for or usage of the above two properties.
Oops. Good catch. Will remove that.
Thanks.
WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock
Date: Tue, 11 Dec 2018 16:52:05 +0800 [thread overview]
Message-ID: <0f424403-50b7-983b-069b-1a7b757bf26a@nvidia.com> (raw)
In-Reply-To: <827e05c8-13b9-fb5e-7bca-1a34b81763b1@nvidia.com>
On 12/7/18 10:57 PM, Jon Hunter wrote:
>
> On 04/12/2018 09:25, Joseph Lo wrote:
>> Enable DFLL clock for Jetson TX1 platform.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> ---
>> .../boot/dts/nvidia/tegra210-p2371-2180.dts | 20 +++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> index 37e3c46e753f..53f497c2b3ff 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> @@ -78,4 +78,24 @@
>> };
>> };
>> };
>> +
>> + clock@70110000 {
>> + status = "okay";
>> + nvidia,pwm-to-pmic;
>> + nvidia,init-uv = <1000000>;
>> + nvidia,align-offset-uv = <708000>;
>> + nvidia,align-step-uv = <19200>;
>> + nvidia,sample-rate = <25000>;
>> + nvidia,droop-ctrl = <0x00000f00>;
>> + nvidia,force-mode = <1>;
>> + nvidia,cf = <6>;
>> + nvidia,ci = <0>;
>> + nvidia,cg = <2>;
>> + nvidia,idle-override;
>> + nvidia,one-shot-calibrate;
>
> I don't see any Documentation for or usage of the above two properties.
Oops. Good catch. Will remove that.
Thanks.
WARNING: multiple messages have this Message-ID (diff)
From: Joseph Lo <josephl@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock
Date: Tue, 11 Dec 2018 16:52:05 +0800 [thread overview]
Message-ID: <0f424403-50b7-983b-069b-1a7b757bf26a@nvidia.com> (raw)
In-Reply-To: <827e05c8-13b9-fb5e-7bca-1a34b81763b1@nvidia.com>
On 12/7/18 10:57 PM, Jon Hunter wrote:
>
> On 04/12/2018 09:25, Joseph Lo wrote:
>> Enable DFLL clock for Jetson TX1 platform.
>>
>> Signed-off-by: Joseph Lo <josephl@nvidia.com>
>> ---
>> .../boot/dts/nvidia/tegra210-p2371-2180.dts | 20 +++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> index 37e3c46e753f..53f497c2b3ff 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
>> @@ -78,4 +78,24 @@
>> };
>> };
>> };
>> +
>> + clock@70110000 {
>> + status = "okay";
>> + nvidia,pwm-to-pmic;
>> + nvidia,init-uv = <1000000>;
>> + nvidia,align-offset-uv = <708000>;
>> + nvidia,align-step-uv = <19200>;
>> + nvidia,sample-rate = <25000>;
>> + nvidia,droop-ctrl = <0x00000f00>;
>> + nvidia,force-mode = <1>;
>> + nvidia,cf = <6>;
>> + nvidia,ci = <0>;
>> + nvidia,cg = <2>;
>> + nvidia,idle-override;
>> + nvidia,one-shot-calibrate;
>
> I don't see any Documentation for or usage of the above two properties.
Oops. Good catch. Will remove that.
Thanks.
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next prev parent reply other threads:[~2018-12-11 8:52 UTC|newest]
Thread overview: 213+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-04 9:25 [PATCH 00/19] Tegra210 DFLL support Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 13:41 ` Jon Hunter
2018-12-07 13:41 ` Jon Hunter
2018-12-07 13:41 ` Jon Hunter
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:59 ` Jon Hunter
2018-12-10 8:59 ` Jon Hunter
2018-12-10 8:59 ` Jon Hunter
2018-12-10 9:31 ` Joseph Lo
2018-12-10 9:31 ` Joseph Lo
2018-12-10 9:44 ` Jon Hunter
2018-12-10 9:44 ` Jon Hunter
2018-12-10 9:44 ` Jon Hunter
2018-12-11 1:28 ` Joseph Lo
2018-12-11 1:28 ` Joseph Lo
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:36 ` Joseph Lo
2018-12-11 9:36 ` Joseph Lo
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 11:52 ` Jon Hunter
2018-12-11 11:52 ` Jon Hunter
2018-12-11 11:52 ` Jon Hunter
2018-12-12 1:52 ` Joseph Lo
2018-12-12 1:52 ` Joseph Lo
2018-12-12 1:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 13:50 ` Jon Hunter
2018-12-07 13:50 ` Jon Hunter
2018-12-07 13:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 03/19] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 15:36 ` Peter De Schrijver
2018-12-04 15:36 ` Peter De Schrijver
2018-12-04 15:36 ` Peter De Schrijver
2018-12-05 3:05 ` Joseph Lo
2018-12-05 3:05 ` Joseph Lo
2018-12-05 3:05 ` Joseph Lo
2018-12-05 9:37 ` Peter De Schrijver
2018-12-05 9:37 ` Peter De Schrijver
2018-12-05 9:37 ` Peter De Schrijver
2018-12-07 13:52 ` Jon Hunter
2018-12-07 13:52 ` Jon Hunter
2018-12-07 13:52 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 15:37 ` Peter De Schrijver
2018-12-04 15:37 ` Peter De Schrijver
2018-12-04 15:37 ` Peter De Schrijver
2018-12-05 3:10 ` Joseph Lo
2018-12-05 3:10 ` Joseph Lo
2018-12-05 3:10 ` Joseph Lo
2018-12-07 13:53 ` Jon Hunter
2018-12-07 13:53 ` Jon Hunter
2018-12-07 13:53 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 13:55 ` Jon Hunter
2018-12-07 13:55 ` Jon Hunter
2018-12-07 13:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 06/19] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:10 ` Jon Hunter
2018-12-07 14:10 ` Jon Hunter
2018-12-07 14:10 ` Jon Hunter
2018-12-11 6:23 ` Joseph Lo
2018-12-11 6:23 ` Joseph Lo
2018-12-11 6:23 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 07/19] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 15:53 ` Peter De Schrijver
2018-12-04 15:53 ` Peter De Schrijver
2018-12-04 15:53 ` Peter De Schrijver
2018-12-05 6:14 ` Joseph Lo
2018-12-05 6:14 ` Joseph Lo
2018-12-05 6:14 ` Joseph Lo
2018-12-07 14:26 ` Jon Hunter
2018-12-07 14:26 ` Jon Hunter
2018-12-07 14:26 ` Jon Hunter
2018-12-11 6:36 ` Joseph Lo
2018-12-11 6:36 ` Joseph Lo
2018-12-11 6:36 ` Joseph Lo
2018-12-07 15:09 ` Jon Hunter
2018-12-07 15:09 ` Jon Hunter
2018-12-07 15:09 ` Jon Hunter
2018-12-11 6:37 ` Joseph Lo
2018-12-11 6:37 ` Joseph Lo
2018-12-11 6:37 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 15:46 ` Peter De Schrijver
2018-12-04 15:46 ` Peter De Schrijver
2018-12-04 15:46 ` Peter De Schrijver
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:51 ` Joseph Lo
2018-12-05 6:51 ` Joseph Lo
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:30 ` Joseph Lo
2018-12-05 9:30 ` Joseph Lo
2018-12-07 14:34 ` Jon Hunter
2018-12-07 14:34 ` Jon Hunter
2018-12-07 14:34 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:39 ` Jon Hunter
2018-12-07 14:39 ` Jon Hunter
2018-12-07 14:39 ` Jon Hunter
2018-12-11 7:34 ` Joseph Lo
2018-12-11 7:34 ` Joseph Lo
2018-12-11 7:34 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 10/19] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:40 ` Jon Hunter
2018-12-07 14:40 ` Jon Hunter
2018-12-07 14:40 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:49 ` Jon Hunter
2018-12-07 14:49 ` Jon Hunter
2018-12-07 14:49 ` Jon Hunter
2018-12-11 8:48 ` Joseph Lo
2018-12-11 8:48 ` Joseph Lo
2018-12-11 8:48 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 12/19] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-05 3:25 ` Joseph Lo
2018-12-05 3:25 ` Joseph Lo
2018-12-05 3:25 ` Joseph Lo
2018-12-07 14:50 ` Jon Hunter
2018-12-07 14:50 ` Jon Hunter
2018-12-07 14:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 13/19] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-07 14:54 ` Jon Hunter
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 14/19] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-07 14:54 ` Jon Hunter
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 15/19] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:55 ` Jon Hunter
2018-12-07 14:55 ` Jon Hunter
2018-12-07 14:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 14:57 ` Jon Hunter
2018-12-07 14:57 ` Jon Hunter
2018-12-07 14:57 ` Jon Hunter
2018-12-11 8:52 ` Joseph Lo [this message]
2018-12-11 8:52 ` Joseph Lo
2018-12-11 8:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 17/19] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-07 15:03 ` Jon Hunter
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-07 15:03 ` Jon Hunter
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 19/19] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-04 9:25 ` Joseph Lo
2018-12-07 15:04 ` Jon Hunter
2018-12-07 15:04 ` Jon Hunter
2018-12-07 15:04 ` Jon Hunter
2018-12-04 15:10 ` [PATCH 00/19] Tegra210 DFLL support Thierry Reding
2018-12-04 15:10 ` Thierry Reding
2018-12-05 6:11 ` Joseph Lo
2018-12-05 6:11 ` Joseph Lo
2018-12-05 6:11 ` Joseph Lo
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