From: Geert Uytterhoeven <geert+renesas@glider.be> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Magnus Damm <magnus.damm@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Ulf Hansson <ulf.hansson@linaro.org> Cc: "Cong Dang" <cong.dang.xn@renesas.com>, "Duy Nguyen" <duy.nguyen.rh@renesas.com>, "Hai Pham" <hai.pham.ud@renesas.com>, "Linh Phung" <linh.phung.jy@renesas.com>, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se> Subject: [PATCH v2 02/15] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions Date: Thu, 25 Jan 2024 16:34:30 +0100 [thread overview] Message-ID: <11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be> (raw) In-Reply-To: <cover.1706194617.git.geert+renesas@glider.be> From: Duy Nguyen <duy.nguyen.rh@renesas.com> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- v2: - Add Reviewed-by, - Add vendor-prefix to file name and update include guard. Changes compared to the BSP: - Drop POST* clocks, as they are internal clocks. --- .../clock/renesas,r8a779h0-cpg-mssr.h | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 0000000000000000..7ab6cfbaf9010326 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert+renesas@glider.be> To: Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Magnus Damm <magnus.damm@gmail.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Ulf Hansson <ulf.hansson@linaro.org> Cc: "Cong Dang" <cong.dang.xn@renesas.com>, "Duy Nguyen" <duy.nguyen.rh@renesas.com>, "Hai Pham" <hai.pham.ud@renesas.com>, "Linh Phung" <linh.phung.jy@renesas.com>, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se> Subject: [PATCH v2 02/15] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions Date: Thu, 25 Jan 2024 16:34:30 +0100 [thread overview] Message-ID: <11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be> (raw) In-Reply-To: <cover.1706194617.git.geert+renesas@glider.be> From: Duy Nguyen <duy.nguyen.rh@renesas.com> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- v2: - Add Reviewed-by, - Add vendor-prefix to file name and update include guard. Changes compared to the BSP: - Drop POST* clocks, as they are internal clocks. --- .../clock/renesas,r8a779h0-cpg-mssr.h | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 0000000000000000..7ab6cfbaf9010326 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-25 15:35 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-25 15:34 [PATCH v2 00/15] arm64: renesas: Add R-Car V4M and Gray Hawk Single support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 15:34 ` [PATCH v2 01/15] dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven [this message] 2024-01-25 15:34 ` [PATCH v2 02/15] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions Geert Uytterhoeven 2024-01-26 10:16 ` Krzysztof Kozlowski 2024-01-26 10:16 ` Krzysztof Kozlowski 2024-01-25 15:34 ` [PATCH v2 03/15] dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 15:34 ` [PATCH v2 04/15] dt-bindings: power: Add r8a779h0 SYSC power domain definitions Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-26 10:16 ` Krzysztof Kozlowski 2024-01-26 10:16 ` Krzysztof Kozlowski 2024-01-25 15:34 ` [PATCH v2 05/15] dt-bindings: reset: renesas,rst: Document R-Car V4M support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 15:34 ` [PATCH v2 06/15] dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 15:34 ` [PATCH v2 07/15] clk: renesas: rcar-gen4: Add support for FRQCRC1 Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 15:34 ` [PATCH v2 08/15] clk: renesas: cpg-mssr: Add support for R-Car V4M Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 18:44 ` Niklas Söderlund 2024-01-25 18:44 ` Niklas Söderlund 2024-01-25 15:34 ` [PATCH v2 09/15] pmdomain: renesas: r8a779h0-sysc: Add r8a779h0 support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 18:46 ` Niklas Söderlund 2024-01-25 18:46 ` Niklas Söderlund 2024-01-26 8:13 ` Geert Uytterhoeven 2024-01-26 8:13 ` Geert Uytterhoeven 2024-01-25 15:34 ` [PATCH v2 10/15] soc: renesas: Introduce ARCH_RCAR_GEN4 Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 18:23 ` Niklas Söderlund 2024-01-25 18:23 ` Niklas Söderlund 2024-01-25 15:34 ` [PATCH v2 11/15] soc: renesas: Identify R-Car V4M Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 18:25 ` Niklas Söderlund 2024-01-25 18:25 ` Niklas Söderlund 2024-01-25 15:34 ` [PATCH v2 12/15] soc: renesas: rcar-rst: Add support for " Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 18:30 ` Niklas Söderlund 2024-01-25 18:30 ` Niklas Söderlund 2024-01-25 15:34 ` [PATCH v2 13/15] arm64: dts: renesas: Add Renesas R8A779H0 SoC support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 19:15 ` Niklas Söderlund 2024-01-25 19:15 ` Niklas Söderlund 2024-01-25 15:34 ` [PATCH v2 14/15] arm64: dts: renesas: Add Gray Hawk Single board support Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-25 19:16 ` Niklas Söderlund 2024-01-25 19:16 ` Niklas Söderlund 2024-01-25 15:34 ` [PATCH v2 15/15] arm64: defconfig: Enable R8A779H0 SoC Geert Uytterhoeven 2024-01-25 15:34 ` Geert Uytterhoeven 2024-01-30 13:11 ` [PATCH v2 00/15] arm64: renesas: Add R-Car V4M and Gray Hawk Single support Ulf Hansson 2024-01-30 13:11 ` Ulf Hansson 2024-01-31 14:56 ` Geert Uytterhoeven 2024-01-31 14:56 ` Geert Uytterhoeven 2024-02-14 8:35 ` Geert Uytterhoeven 2024-02-14 8:35 ` Geert Uytterhoeven 2024-02-14 9:30 ` Ulf Hansson 2024-02-14 9:30 ` Ulf Hansson
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