Re: [PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
To: "vkoul@kernel.org" <vkoul@kernel.org>,
	"richard.leitner@linux.dev" <richard.leitner@linux.dev>,
	"alexander.stein@ew.tq-group.com"
	<alexander.stein@ew.tq-group.com>,
	"robh@kernel.org" <robh@kernel.org>,
	"l.stach@pengutronix.de" <l.stach@pengutronix.de>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"hongxing.zhu@nxp.com" <hongxing.zhu@nxp.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"marex@denx.de" <marex@denx.de>
Cc: "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-imx@nxp.com" <linux-imx@nxp.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 3/7] arm64: dts: imx8mp-evk: Add PCIe support
Date: Wed, 31 Aug 2022 10:18:10 +0000	[thread overview]
Message-ID: <1218d5afbbf18f8b5ab9013e08fde84a787d8df3.camel@toradex.com> (raw)
In-Reply-To: <1661845564-11373-4-git-send-email-hongxing.zhu@nxp.com>

On Tue, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> Add PCIe support on i.MX8MP EVK board.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 ++++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index f6b017ab5f53..defc92a8bb60 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -5,6 +5,7 @@
>  
>  /dts-v1/;
>  
> +#include <dt-bindings/phy/phy-imx8-pcie.h>
>  #include "imx8mp.dtsi"
>  
>  / {
> @@ -33,6 +34,12 @@ memory@40000000 {
>                       <0x1 0x00000000 0 0xc0000000>;
>         };
>  
> +       pcie0_refclk: pcie0-refclk {
> +               compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <100000000>;
> +       };
> +
>         reg_can1_stby: regulator-can1-stby {
>                 compatible = "regulator-fixed";
>                 regulator-name = "can1-stby";
> @@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
>                 enable-active-high;
>         };
>  
> +       reg_pcie0: regulator-pcie {
> +               compatible = "regulator-fixed";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&pinctrl_pcie0_reg>;
> +               regulator-name = "MPCIE_3V3";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +               gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +       };
> +
>         reg_usdhc2_vmmc: regulator-usdhc2 {
>                 compatible = "regulator-fixed";
>                 pinctrl-names = "default";
> @@ -350,6 +368,28 @@ &i2c5 {
>          */
>  };
>  
> +&pcie_phy {
> +       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> +       clocks = <&pcie0_refclk>;
> +       clock-names = "ref";
> +       status = "okay";
> +};
> +
> +&pcie{

Missing space before that curly brace.

> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_pcie0>;
> +       reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> +       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +                <&clk IMX8MP_CLK_PCIE_ROOT>,
> +                <&clk IMX8MP_CLK_HSIO_AXI>;
> +       clock-names = "pcie", "pcie_aux", "pcie_bus";
> +       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
> +       assigned-clock-rates = <10000000>;
> +       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
> +       vpcie-supply = <&reg_pcie0>;
> +       status = "okay";
> +};
> +
>  &snvs_pwrkey {
>         status = "okay";
>  };
> @@ -502,6 +542,19 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
>                 >;
>         };
>  
> +       pinctrl_pcie0: pcie0grp {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x61 /* open drain, pull up */
> +                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x41
> +               >;
> +       };
> +
> +       pinctrl_pcie0_reg: pcie0reggrp {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x41
> +               >;
> +       };
> +
>         pinctrl_pmic: pmicgrp {
>                 fsl,pins = <
>                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x000001c0