From: "Heiko Stübner" <heiko@sntech.de>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: mturquette@baylibre.com, sboyd@codeaurora.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
dianders@chromium.org, briannorris@chromium.org,
huangtao@rock-chips.com, zhangqing@rock-chips.com
Subject: Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies
Date: Thu, 04 Aug 2016 21:19:08 +0200 [thread overview]
Message-ID: <12790025.3tRiQgk9GG@diego> (raw)
In-Reply-To: <1470122579-32083-1-git-send-email-zhengxing@rock-chips.com>
Hi Xing,
Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
> We need to support various display resolutions for external
> display devices like HDMI/DP, the frac mode can help us to
> acquire almost any frequencies, and need higher VCOs to reduce
> clock jitters.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
why does this need to be a separate rate array and cannot live in the general
pll rate array?
The plls are general purpose, so we shouldn't limit them arbitarily.
I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present
in both arrays but have different settings. As your patch description says
that these settings reduce clock jitter, wouldn't the general frequencies also
profit from merging these new values into the general rate array?
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies
Date: Thu, 04 Aug 2016 21:19:08 +0200 [thread overview]
Message-ID: <12790025.3tRiQgk9GG@diego> (raw)
In-Reply-To: <1470122579-32083-1-git-send-email-zhengxing@rock-chips.com>
Hi Xing,
Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
> We need to support various display resolutions for external
> display devices like HDMI/DP, the frac mode can help us to
> acquire almost any frequencies, and need higher VCOs to reduce
> clock jitters.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
why does this need to be a separate rate array and cannot live in the general
pll rate array?
The plls are general purpose, so we shouldn't limit them arbitarily.
I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present
in both arrays but have different settings. As your patch description says
that these settings reduce clock jitter, wouldn't the general frequencies also
profit from merging these new values into the general rate array?
Heiko
next prev parent reply other threads:[~2016-08-04 19:19 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-02 7:19 [PATCH v3 0/7] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` [PATCH v3 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` [PATCH v3 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-04 19:10 ` Heiko Stübner
2016-08-04 19:10 ` Heiko Stübner
2016-08-05 8:34 ` Frank Wang
2016-08-05 8:34 ` Frank Wang
2016-08-05 8:34 ` Frank Wang
2016-08-05 16:05 ` Heiko Stübner
2016-08-05 16:05 ` Heiko Stübner
2016-08-05 16:05 ` Heiko Stübner
2016-08-08 9:55 ` Frank Wang
2016-08-08 9:55 ` Frank Wang
2016-08-16 6:34 ` Frank Wang
2016-08-16 6:34 ` Frank Wang
2016-08-02 7:19 ` [PATCH v3 3/7] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-12 16:30 ` Heiko Stübner
2016-08-12 16:30 ` Heiko Stübner
2016-08-02 7:19 ` [PATCH v3 4/7] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-12 8:05 ` Heiko Stübner
2016-08-12 8:05 ` Heiko Stübner
2016-08-12 8:05 ` Heiko Stübner
2016-08-02 7:22 ` [PATCH v3 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-04 19:05 ` Heiko Stübner
2016-08-04 19:05 ` Heiko Stübner
2016-08-02 7:22 ` [PATCH v3 6/7] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-04 19:06 ` Heiko Stübner
2016-08-04 19:06 ` Heiko Stübner
2016-08-02 7:22 ` [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-04 19:19 ` Heiko Stübner [this message]
2016-08-04 19:19 ` Heiko Stübner
2016-08-05 2:26 ` Xing Zheng
2016-08-05 2:26 ` Xing Zheng
2016-08-05 8:48 ` Heiko Stübner
2016-08-05 8:48 ` Heiko Stübner
2016-08-05 8:48 ` Heiko Stübner
2016-08-05 13:23 ` Xing Zheng
2016-08-05 13:23 ` Xing Zheng
2016-08-05 13:23 ` Xing Zheng
2016-08-05 13:26 ` Heiko Stübner
2016-08-05 13:26 ` Heiko Stübner
2016-08-05 13:26 ` Heiko Stübner
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