From: "Heiko Stübner" <heiko@sntech.de>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org,
briannorris@chromium.org, huangtao@rock-chips.com,
zhangqing@rock-chips.com,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/7] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src
Date: Fri, 12 Aug 2016 18:30:16 +0200 [thread overview]
Message-ID: <1511923.bnfOuYbtIQ@diego> (raw)
In-Reply-To: <1470122401-31934-4-git-send-email-zhengxing@rock-chips.com>
Am Dienstag, 2. August 2016, 15:19:57 schrieb Xing Zheng:
> Sorry to refer incorrect clock diagram, we double check it that the bits
> configuration of the Xpll_aclk_perihp_src need to be fixed:
> bit 1 - shows aclk_perihp_cpll_src_en
> bit 0 - shows aclk_perihp_gpll_src_en
>
> Through the testing that plug/unplug the USB ethernet cable on the RK3399
> kevin board.
>
> 1. the hclk_host0 and hclk_host1 are endpoint clocks:
> cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0
>
> | --> ... ---> |
>
> gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1
>
> 2. there is no clock below the cpll_aclk_perihp_src,
> and the hclk_hostX are below the gpll_aclk_perihp_src:
> pll_cpll 1 1 800000000
> 0 0 cpll 7 19 800000000
> 0 0 cpll_aclk_perihp_src 0 0 800000000 0 0
> ...
> pll_gpll 1 1 594000000
> 0 0 gpll 10 10 594000000
> 0 0 gpll_aclk_perihp_src 2 2 594000000 0 0
> hclk_perihp 5 5 74250000 0 0
> hclk_host1_arb 2 2 74250000 0 0 hclk_host1
> 2 2 74250000 0 0 hclk_host0_arb 2
> 2 74250000 0 0 hclk_host0 2 2
> 74250000 0 0
>
> 3. by default, G5[0] and G5[1] are enabled:
> localhost ~ # mem r 0xff760314
> 0x000003e0
>
> 4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet
> cable, the DUT still works well:
> localhost ~ # mem w 0xff760314 0xffff03e2
> localhost ~ # mem r 0xff760314
> 0x000003e2
> plug/unplug, the work statue is ok
>
> 5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet
> cable, the DUT will be crashed:
> localhost ~ # mem w 0xff760314 0xffff03e1
> localhost ~ # mem r 0xff760314
> 0x000003e1
> plug/unplug, the DUT is crashed
>
> Summary:
> bit 1 - shows aclk_perihp_cpll_src_en
> bit 0 - shows aclk_perihp_gpll_src_en
>
> Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's
> {c,g}pll_aclk_perihp_src") Signed-off-by: Xing Zheng
> <zhengxing@rock-chips.com>
applied to my clk-fixes branch for 4.8
Thanks
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/7] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src
Date: Fri, 12 Aug 2016 18:30:16 +0200 [thread overview]
Message-ID: <1511923.bnfOuYbtIQ@diego> (raw)
In-Reply-To: <1470122401-31934-4-git-send-email-zhengxing@rock-chips.com>
Am Dienstag, 2. August 2016, 15:19:57 schrieb Xing Zheng:
> Sorry to refer incorrect clock diagram, we double check it that the bits
> configuration of the Xpll_aclk_perihp_src need to be fixed:
> bit 1 - shows aclk_perihp_cpll_src_en
> bit 0 - shows aclk_perihp_gpll_src_en
>
> Through the testing that plug/unplug the USB ethernet cable on the RK3399
> kevin board.
>
> 1. the hclk_host0 and hclk_host1 are endpoint clocks:
> cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0
>
> | --> ... ---> |
>
> gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1
>
> 2. there is no clock below the cpll_aclk_perihp_src,
> and the hclk_hostX are below the gpll_aclk_perihp_src:
> pll_cpll 1 1 800000000
> 0 0 cpll 7 19 800000000
> 0 0 cpll_aclk_perihp_src 0 0 800000000 0 0
> ...
> pll_gpll 1 1 594000000
> 0 0 gpll 10 10 594000000
> 0 0 gpll_aclk_perihp_src 2 2 594000000 0 0
> hclk_perihp 5 5 74250000 0 0
> hclk_host1_arb 2 2 74250000 0 0 hclk_host1
> 2 2 74250000 0 0 hclk_host0_arb 2
> 2 74250000 0 0 hclk_host0 2 2
> 74250000 0 0
>
> 3. by default, G5[0] and G5[1] are enabled:
> localhost ~ # mem r 0xff760314
> 0x000003e0
>
> 4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet
> cable, the DUT still works well:
> localhost ~ # mem w 0xff760314 0xffff03e2
> localhost ~ # mem r 0xff760314
> 0x000003e2
> plug/unplug, the work statue is ok
>
> 5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet
> cable, the DUT will be crashed:
> localhost ~ # mem w 0xff760314 0xffff03e1
> localhost ~ # mem r 0xff760314
> 0x000003e1
> plug/unplug, the DUT is crashed
>
> Summary:
> bit 1 - shows aclk_perihp_cpll_src_en
> bit 0 - shows aclk_perihp_gpll_src_en
>
> Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's
> {c,g}pll_aclk_perihp_src") Signed-off-by: Xing Zheng
> <zhengxing@rock-chips.com>
applied to my clk-fixes branch for 4.8
Thanks
Heiko
next prev parent reply other threads:[~2016-08-12 16:30 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-02 7:19 [PATCH v3 0/7] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` [PATCH v3 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` [PATCH v3 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-04 19:10 ` Heiko Stübner
2016-08-04 19:10 ` Heiko Stübner
2016-08-05 8:34 ` Frank Wang
2016-08-05 8:34 ` Frank Wang
2016-08-05 8:34 ` Frank Wang
2016-08-05 16:05 ` Heiko Stübner
2016-08-05 16:05 ` Heiko Stübner
2016-08-05 16:05 ` Heiko Stübner
2016-08-08 9:55 ` Frank Wang
2016-08-08 9:55 ` Frank Wang
2016-08-16 6:34 ` Frank Wang
2016-08-16 6:34 ` Frank Wang
2016-08-02 7:19 ` [PATCH v3 3/7] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-12 16:30 ` Heiko Stübner [this message]
2016-08-12 16:30 ` Heiko Stübner
2016-08-02 7:19 ` [PATCH v3 4/7] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-02 7:19 ` Xing Zheng
2016-08-12 8:05 ` Heiko Stübner
2016-08-12 8:05 ` Heiko Stübner
2016-08-12 8:05 ` Heiko Stübner
2016-08-02 7:22 ` [PATCH v3 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-04 19:05 ` Heiko Stübner
2016-08-04 19:05 ` Heiko Stübner
2016-08-02 7:22 ` [PATCH v3 6/7] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-04 19:06 ` Heiko Stübner
2016-08-04 19:06 ` Heiko Stübner
2016-08-02 7:22 ` [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng
2016-08-02 7:22 ` Xing Zheng
2016-08-04 19:19 ` Heiko Stübner
2016-08-04 19:19 ` Heiko Stübner
2016-08-05 2:26 ` Xing Zheng
2016-08-05 2:26 ` Xing Zheng
2016-08-05 8:48 ` Heiko Stübner
2016-08-05 8:48 ` Heiko Stübner
2016-08-05 8:48 ` Heiko Stübner
2016-08-05 13:23 ` Xing Zheng
2016-08-05 13:23 ` Xing Zheng
2016-08-05 13:23 ` Xing Zheng
2016-08-05 13:26 ` Heiko Stübner
2016-08-05 13:26 ` Heiko Stübner
2016-08-05 13:26 ` Heiko Stübner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1511923.bnfOuYbtIQ@diego \
--to=heiko@sntech.de \
--cc=briannorris@chromium.org \
--cc=dianders@chromium.org \
--cc=huangtao@rock-chips.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=mturquette@baylibre.com \
--cc=sboyd@codeaurora.org \
--cc=zhangqing@rock-chips.com \
--cc=zhengxing@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.