From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 11/18] drm/i915: convert CPU M/N timings to transcoder
Date: Tue, 23 Oct 2012 18:30:01 -0200 [thread overview]
Message-ID: <1351024208-3489-12-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1351024208-3489-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++--------
drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
drivers/gpu/drm/i915/intel_dp.c | 10 ++++++----
3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ec99e3..bf411dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3305,14 +3305,14 @@
#define _PIPEB_LINK_M2 0x61048
#define _PIPEB_LINK_N2 0x6104c
-#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
-#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
-#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
-#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
-#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
-#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
-#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
-#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
+#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2d1f74c..b616a1c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4995,7 +4995,7 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
struct intel_encoder *intel_encoder, *edp_encoder = NULL;
struct fdi_m_n m_n = {0};
int target_clock, pixel_multiplier, lane, link_bw;
@@ -5058,10 +5058,10 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
&m_n);
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
}
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fe4dc35..f15ea22 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -777,6 +777,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
int lane_count = 4;
struct intel_dp_m_n m_n;
int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
/*
* Find the lane count in the intel_encoder private
@@ -801,10 +802,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
mode->clock, adjusted_mode->clock, &m_n);
if (IS_HASWELL(dev)) {
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
+ TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
} else if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
--
1.7.11.4
next prev parent reply other threads:[~2012-10-23 20:30 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-23 20:29 [PATCH 00/18] Haswell eDP enablement v3 Paulo Zanoni
2012-10-23 20:29 ` [PATCH 01/18] drm/i915: fork a Haswell version of ironlake_crtc_{enable, disable} Paulo Zanoni
2012-10-24 13:15 ` Rodrigo Vivi
2012-10-25 11:03 ` Jani Nikula
2012-10-23 20:29 ` [PATCH 02/18] drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable Paulo Zanoni
2012-10-24 13:18 ` Rodrigo Vivi
2012-10-24 13:31 ` Paulo Zanoni
2012-10-23 20:29 ` [PATCH 03/18] drm/i915: simplify intel_crtc_driving_pch Paulo Zanoni
2012-10-25 11:13 ` Jani Nikula
2012-10-25 12:04 ` Paulo Zanoni
2012-10-25 12:37 ` Paulo Zanoni
2012-10-23 20:29 ` [PATCH 04/18] drm/i915: don't call Haswell PCH code when we can't or don't need Paulo Zanoni
2012-10-25 12:18 ` Jani Nikula
2012-10-23 20:29 ` [PATCH 05/18] drm/i915: add TRANSCODER_EDP Paulo Zanoni
2012-10-24 14:50 ` Lespiau, Damien
2012-10-24 16:33 ` Paulo Zanoni
2012-10-24 16:43 ` Daniel Vetter
2012-10-24 17:59 ` Paulo Zanoni
2012-10-25 10:23 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 06/18] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
2012-10-24 14:55 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 07/18] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
2012-10-24 15:12 ` Lespiau, Damien
2012-10-24 15:30 ` Lespiau, Damien
2012-10-24 16:44 ` Paulo Zanoni
2012-10-24 18:06 ` Paulo Zanoni
2012-10-25 10:24 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
2012-10-24 12:38 ` Daniel Vetter
2012-10-24 15:45 ` Lespiau, Damien
2012-10-24 15:50 ` Daniel Vetter
2012-10-24 18:09 ` Paulo Zanoni
2012-10-25 10:26 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 09/18] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
2012-10-25 11:12 ` Lespiau, Damien
2012-10-23 20:30 ` [PATCH 10/18] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
2012-10-25 11:09 ` Lespiau, Damien
2012-10-23 20:30 ` Paulo Zanoni [this message]
2012-10-25 11:10 ` [PATCH 11/18] drm/i915: convert CPU M/N timings " Lespiau, Damien
2012-10-23 20:30 ` [PATCH 12/18] drm/i915: convert pipe timing definitions " Paulo Zanoni
2012-10-25 11:12 ` Lespiau, Damien
2012-10-23 20:30 ` [PATCH 13/18] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
2012-10-23 20:44 ` Daniel Vetter
2012-10-24 13:34 ` Paulo Zanoni
2012-10-24 15:24 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 14/18] drm/i915: select the correct pipe " Paulo Zanoni
2012-10-24 13:58 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 15/18] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
2012-10-24 14:07 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 16/18] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
2012-10-24 14:11 ` Rodrigo Vivi
2012-10-24 14:22 ` Daniel Vetter
2012-10-24 14:43 ` Paulo Zanoni
2012-10-23 20:30 ` [PATCH 17/18] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-24 15:20 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 18/18] drm/i915: enable DDI eDP Paulo Zanoni
2012-10-24 14:24 ` Rodrigo Vivi
2012-10-25 20:17 ` Daniel Vetter
2012-10-24 13:31 ` [PATCH 02-1/18] drm/i915: fix checks inside ironlake_crtc_{enable, disable} Paulo Zanoni
2012-10-24 13:32 ` [PATCH 02-2/18] drm/i915: fix checks inside haswell_crtc_{enable, disable} Paulo Zanoni
2012-10-25 11:07 ` Jani Nikula
2012-10-25 11:04 ` [PATCH 02-1/18] drm/i915: fix checks inside ironlake_crtc_{enable, disable} Jani Nikula
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