From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 12/18] drm/i915: convert pipe timing definitions to transcoder
Date: Tue, 23 Oct 2012 18:30:02 -0200 [thread overview]
Message-ID: <1351024208-3489-13-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1351024208-3489-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 8 +++++---
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
drivers/gpu/drm/i915/intel_display.c | 37 ++++++++++++++++++------------------
3 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6036d21..b92e6bfb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,6 +185,8 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
int vbl_start, vbl_end, htotal, vtotal;
bool in_vbl = true;
int ret = 0;
+ enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
+ pipe);
if (!i915_pipe_enabled(dev, pipe)) {
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
@@ -193,7 +195,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
}
/* Get vtotal. */
- vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
+ vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
if (INTEL_INFO(dev)->gen >= 4) {
/* No obvious pixelcount register. Only query vertical
@@ -213,13 +215,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
*/
position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
- htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
+ htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
*vpos = position / htotal;
*hpos = position - (*vpos * htotal);
}
/* Query vblank area. */
- vbl = I915_READ(VBLANK(pipe));
+ vbl = I915_READ(VBLANK(cpu_transcoder));
/* Test position against vblank region. */
vbl_start = vbl & 0x1fff;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf411dd..c475310 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1568,14 +1568,14 @@
#define _VSYNCSHIFT_B 0x61028
-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
/* VGA port control */
#define ADPA 0x61100
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b616a1c..1b72f36 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4488,6 +4488,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t vsyncshift;
if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -4501,25 +4502,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
}
if (INTEL_INFO(dev)->gen > 3)
- I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
+ I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
- I915_WRITE(HTOTAL(pipe),
+ I915_WRITE(HTOTAL(cpu_transcoder),
(adjusted_mode->crtc_hdisplay - 1) |
((adjusted_mode->crtc_htotal - 1) << 16));
- I915_WRITE(HBLANK(pipe),
+ I915_WRITE(HBLANK(cpu_transcoder),
(adjusted_mode->crtc_hblank_start - 1) |
((adjusted_mode->crtc_hblank_end - 1) << 16));
- I915_WRITE(HSYNC(pipe),
+ I915_WRITE(HSYNC(cpu_transcoder),
(adjusted_mode->crtc_hsync_start - 1) |
((adjusted_mode->crtc_hsync_end - 1) << 16));
- I915_WRITE(VTOTAL(pipe),
+ I915_WRITE(VTOTAL(cpu_transcoder),
(adjusted_mode->crtc_vdisplay - 1) |
((adjusted_mode->crtc_vtotal - 1) << 16));
- I915_WRITE(VBLANK(pipe),
+ I915_WRITE(VBLANK(cpu_transcoder),
(adjusted_mode->crtc_vblank_start - 1) |
((adjusted_mode->crtc_vblank_end - 1) << 16));
- I915_WRITE(VSYNC(pipe),
+ I915_WRITE(VSYNC(cpu_transcoder),
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
@@ -6481,12 +6482,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
struct drm_display_mode *mode;
- int htot = I915_READ(HTOTAL(pipe));
- int hsync = I915_READ(HSYNC(pipe));
- int vtot = I915_READ(VTOTAL(pipe));
- int vsync = I915_READ(VSYNC(pipe));
+ int htot = I915_READ(HTOTAL(cpu_transcoder));
+ int hsync = I915_READ(HSYNC(cpu_transcoder));
+ int vtot = I915_READ(VTOTAL(cpu_transcoder));
+ int vsync = I915_READ(VSYNC(cpu_transcoder));
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -8946,12 +8947,12 @@ intel_display_capture_error_state(struct drm_device *dev)
error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
error->pipe[i].source = I915_READ(PIPESRC(i));
- error->pipe[i].htotal = I915_READ(HTOTAL(i));
- error->pipe[i].hblank = I915_READ(HBLANK(i));
- error->pipe[i].hsync = I915_READ(HSYNC(i));
- error->pipe[i].vtotal = I915_READ(VTOTAL(i));
- error->pipe[i].vblank = I915_READ(VBLANK(i));
- error->pipe[i].vsync = I915_READ(VSYNC(i));
+ error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
+ error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
+ error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
+ error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
+ error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
+ error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
}
return error;
--
1.7.11.4
next prev parent reply other threads:[~2012-10-23 20:30 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-23 20:29 [PATCH 00/18] Haswell eDP enablement v3 Paulo Zanoni
2012-10-23 20:29 ` [PATCH 01/18] drm/i915: fork a Haswell version of ironlake_crtc_{enable, disable} Paulo Zanoni
2012-10-24 13:15 ` Rodrigo Vivi
2012-10-25 11:03 ` Jani Nikula
2012-10-23 20:29 ` [PATCH 02/18] drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable Paulo Zanoni
2012-10-24 13:18 ` Rodrigo Vivi
2012-10-24 13:31 ` Paulo Zanoni
2012-10-23 20:29 ` [PATCH 03/18] drm/i915: simplify intel_crtc_driving_pch Paulo Zanoni
2012-10-25 11:13 ` Jani Nikula
2012-10-25 12:04 ` Paulo Zanoni
2012-10-25 12:37 ` Paulo Zanoni
2012-10-23 20:29 ` [PATCH 04/18] drm/i915: don't call Haswell PCH code when we can't or don't need Paulo Zanoni
2012-10-25 12:18 ` Jani Nikula
2012-10-23 20:29 ` [PATCH 05/18] drm/i915: add TRANSCODER_EDP Paulo Zanoni
2012-10-24 14:50 ` Lespiau, Damien
2012-10-24 16:33 ` Paulo Zanoni
2012-10-24 16:43 ` Daniel Vetter
2012-10-24 17:59 ` Paulo Zanoni
2012-10-25 10:23 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 06/18] drm/i915: convert PIPE_CLK_SEL to transcoder Paulo Zanoni
2012-10-24 14:55 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 07/18] drm/i915: convert DDI_FUNC_CTL " Paulo Zanoni
2012-10-24 15:12 ` Lespiau, Damien
2012-10-24 15:30 ` Lespiau, Damien
2012-10-24 16:44 ` Paulo Zanoni
2012-10-24 18:06 ` Paulo Zanoni
2012-10-25 10:24 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 08/18] drm/i915: check TRANSCODER_EDP on intel_modeset_setup_hw_state Paulo Zanoni
2012-10-24 12:38 ` Daniel Vetter
2012-10-24 15:45 ` Lespiau, Damien
2012-10-24 15:50 ` Daniel Vetter
2012-10-24 18:09 ` Paulo Zanoni
2012-10-25 10:26 ` Lespiau, Damien
2012-10-23 20:29 ` [PATCH 09/18] drm/i915: convert PIPECONF to use transcoder instead of pipe Paulo Zanoni
2012-10-25 11:12 ` Lespiau, Damien
2012-10-23 20:30 ` [PATCH 10/18] drm/i915: convert PIPE_MSA_MISC to transcoder Paulo Zanoni
2012-10-25 11:09 ` Lespiau, Damien
2012-10-23 20:30 ` [PATCH 11/18] drm/i915: convert CPU M/N timings " Paulo Zanoni
2012-10-25 11:10 ` Lespiau, Damien
2012-10-23 20:30 ` Paulo Zanoni [this message]
2012-10-25 11:12 ` [PATCH 12/18] drm/i915: convert pipe timing definitions " Lespiau, Damien
2012-10-23 20:30 ` [PATCH 13/18] drm/i915: implement workaround for VTOTAL when using TRANSCODER_EDP Paulo Zanoni
2012-10-23 20:44 ` Daniel Vetter
2012-10-24 13:34 ` Paulo Zanoni
2012-10-24 15:24 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 14/18] drm/i915: select the correct pipe " Paulo Zanoni
2012-10-24 13:58 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 15/18] drm/i915: set the correct eDP aux channel clock divider on DDI Paulo Zanoni
2012-10-24 14:07 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 16/18] drm/i915: set/unset the DDI eDP backlight Paulo Zanoni
2012-10-24 14:11 ` Rodrigo Vivi
2012-10-24 14:22 ` Daniel Vetter
2012-10-24 14:43 ` Paulo Zanoni
2012-10-23 20:30 ` [PATCH 17/18] drm/i915: turn the eDP DDI panel on/off Paulo Zanoni
2012-10-24 15:20 ` Rodrigo Vivi
2012-10-23 20:30 ` [PATCH 18/18] drm/i915: enable DDI eDP Paulo Zanoni
2012-10-24 14:24 ` Rodrigo Vivi
2012-10-25 20:17 ` Daniel Vetter
2012-10-24 13:31 ` [PATCH 02-1/18] drm/i915: fix checks inside ironlake_crtc_{enable, disable} Paulo Zanoni
2012-10-24 13:32 ` [PATCH 02-2/18] drm/i915: fix checks inside haswell_crtc_{enable, disable} Paulo Zanoni
2012-10-25 11:07 ` Jani Nikula
2012-10-25 11:04 ` [PATCH 02-1/18] drm/i915: fix checks inside ironlake_crtc_{enable, disable} Jani Nikula
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