From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Grant Likely
<grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
Rob Landley <rob-VoJi6FS/r0vR7s880joybQ@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v7 03/12] clk: tegra: Add TEGRA_PLL_BYPASS flag
Date: Fri, 15 Feb 2013 14:36:33 +0200 [thread overview]
Message-ID: <1360931849-7090-4-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-pll.c | 12 ++++++++----
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 3feefb1..4ee6d03 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -171,7 +171,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
clk_pll_enable_lock(pll);
val = pll_readl_base(pll);
- val &= ~PLL_BASE_BYPASS;
+ if (pll->flags & TEGRA_PLL_BYPASS)
+ val &= ~PLL_BASE_BYPASS;
val |= PLL_BASE_ENABLE;
pll_writel_base(val, pll);
@@ -188,7 +189,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
u32 val;
val = pll_readl_base(pll);
- val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+ if (pll->flags & TEGRA_PLL_BYPASS)
+ val &= ~PLL_BASE_BYPASS;
+ val &= ~PLL_BASE_ENABLE;
pll_writel_base(val, pll);
if (pll->flags & TEGRA_PLLM) {
@@ -459,7 +462,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
val = pll_readl_base(pll);
- if (val & PLL_BASE_BYPASS)
+ if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
return parent_rate;
if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -671,6 +674,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
struct tegra_clk_pll *pll;
struct clk *clk;
+ pll_flags |= TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock);
if (IS_ERR(pll))
@@ -692,8 +696,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
- pll_flags |= TEGRA_PLL_LOCK_MISC;
+ pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock);
if (IS_ERR(pll))
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 0a9e088..2697aa8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -184,6 +184,7 @@ struct tegra_clk_pll_params {
* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
* base register.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
*/
struct tegra_clk_pll {
struct clk_hw hw;
@@ -213,6 +214,7 @@ struct tegra_clk_pll {
#define TEGRA_PLL_FIXED BIT(6)
#define TEGRA_PLLE_CONFIGURE BIT(7)
#define TEGRA_PLL_LOCK_MISC BIT(8)
+#define TEGRA_PLL_BYPASS BIT(9)
extern const struct clk_ops tegra_clk_pll_ops;
extern const struct clk_ops tegra_clk_plle_ops;
--
1.7.1
WARNING: multiple messages have this Message-ID (diff)
From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Grant Likely <grant.likely@secretlab.ca>,
Rob Herring <rob.herring@calxeda.com>,
Rob Landley <rob@landley.net>,
Stephen Warren <swarren@wwwdotorg.org>,
Russell King <linux@arm.linux.org.uk>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Simon Glass <sjg@chromium.org>,
Mike Turquette <mturquette@linaro.org>,
Joseph Lo <josephl@nvidia.com>,
<devicetree-discuss@lists.ozlabs.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 03/12] clk: tegra: Add TEGRA_PLL_BYPASS flag
Date: Fri, 15 Feb 2013 14:36:33 +0200 [thread overview]
Message-ID: <1360931849-7090-4-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver@nvidia.com>
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 12 ++++++++----
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 3feefb1..4ee6d03 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -171,7 +171,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
clk_pll_enable_lock(pll);
val = pll_readl_base(pll);
- val &= ~PLL_BASE_BYPASS;
+ if (pll->flags & TEGRA_PLL_BYPASS)
+ val &= ~PLL_BASE_BYPASS;
val |= PLL_BASE_ENABLE;
pll_writel_base(val, pll);
@@ -188,7 +189,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
u32 val;
val = pll_readl_base(pll);
- val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+ if (pll->flags & TEGRA_PLL_BYPASS)
+ val &= ~PLL_BASE_BYPASS;
+ val &= ~PLL_BASE_ENABLE;
pll_writel_base(val, pll);
if (pll->flags & TEGRA_PLLM) {
@@ -459,7 +462,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
val = pll_readl_base(pll);
- if (val & PLL_BASE_BYPASS)
+ if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
return parent_rate;
if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -671,6 +674,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
struct tegra_clk_pll *pll;
struct clk *clk;
+ pll_flags |= TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock);
if (IS_ERR(pll))
@@ -692,8 +696,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
- pll_flags |= TEGRA_PLL_LOCK_MISC;
+ pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock);
if (IS_ERR(pll))
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 0a9e088..2697aa8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -184,6 +184,7 @@ struct tegra_clk_pll_params {
* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
* base register.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
*/
struct tegra_clk_pll {
struct clk_hw hw;
@@ -213,6 +214,7 @@ struct tegra_clk_pll {
#define TEGRA_PLL_FIXED BIT(6)
#define TEGRA_PLLE_CONFIGURE BIT(7)
#define TEGRA_PLL_LOCK_MISC BIT(8)
+#define TEGRA_PLL_BYPASS BIT(9)
extern const struct clk_ops tegra_clk_pll_ops;
extern const struct clk_ops tegra_clk_plle_ops;
--
1.7.1
WARNING: multiple messages have this Message-ID (diff)
From: pdeschrijver@nvidia.com (Peter De Schrijver)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 03/12] clk: tegra: Add TEGRA_PLL_BYPASS flag
Date: Fri, 15 Feb 2013 14:36:33 +0200 [thread overview]
Message-ID: <1360931849-7090-4-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver@nvidia.com>
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 12 ++++++++----
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 3feefb1..4ee6d03 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -171,7 +171,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
clk_pll_enable_lock(pll);
val = pll_readl_base(pll);
- val &= ~PLL_BASE_BYPASS;
+ if (pll->flags & TEGRA_PLL_BYPASS)
+ val &= ~PLL_BASE_BYPASS;
val |= PLL_BASE_ENABLE;
pll_writel_base(val, pll);
@@ -188,7 +189,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
u32 val;
val = pll_readl_base(pll);
- val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+ if (pll->flags & TEGRA_PLL_BYPASS)
+ val &= ~PLL_BASE_BYPASS;
+ val &= ~PLL_BASE_ENABLE;
pll_writel_base(val, pll);
if (pll->flags & TEGRA_PLLM) {
@@ -459,7 +462,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
val = pll_readl_base(pll);
- if (val & PLL_BASE_BYPASS)
+ if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
return parent_rate;
if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -671,6 +674,7 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
struct tegra_clk_pll *pll;
struct clk *clk;
+ pll_flags |= TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock);
if (IS_ERR(pll))
@@ -692,8 +696,8 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
{
struct tegra_clk_pll *pll;
struct clk *clk;
- pll_flags |= TEGRA_PLL_LOCK_MISC;
+ pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
freq_table, lock);
if (IS_ERR(pll))
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 0a9e088..2697aa8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -184,6 +184,7 @@ struct tegra_clk_pll_params {
* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
* base register.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
*/
struct tegra_clk_pll {
struct clk_hw hw;
@@ -213,6 +214,7 @@ struct tegra_clk_pll {
#define TEGRA_PLL_FIXED BIT(6)
#define TEGRA_PLLE_CONFIGURE BIT(7)
#define TEGRA_PLL_LOCK_MISC BIT(8)
+#define TEGRA_PLL_BYPASS BIT(9)
extern const struct clk_ops tegra_clk_pll_ops;
extern const struct clk_ops tegra_clk_plle_ops;
--
1.7.1
next prev parent reply other threads:[~2013-02-15 12:36 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-15 12:36 [PATCH v7 00/12] Tegra114 clockframework Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 01/12] clk: tegra: provide dummy cpu car ops Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
[not found] ` <1360931849-7090-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-15 12:36 ` [PATCH v7 02/12] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver [this message]
2013-02-15 12:36 ` [PATCH v7 03/12] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 04/12] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 05/12] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 08/12] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 09/12] clk: tegra: Implement clocks for Tegra114 Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 10/12] clk: tegra: devicetree match for nvidia, tegra114-car Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 10/12] clk: tegra: devicetree match for nvidia,tegra114-car Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 11/12] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 12/12] clk: tegra: Remove forced clk_enable of uartd Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-19 18:39 ` [PATCH v7 00/12] Tegra114 clockframework Stephen Warren
2013-02-19 18:39 ` Stephen Warren
2013-02-19 18:39 ` Stephen Warren
[not found] ` <5123C6E7.9070407-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-02-19 18:50 ` Mike Turquette
2013-02-19 18:50 ` Mike Turquette
2013-02-19 18:50 ` Mike Turquette
2013-04-04 17:52 ` Peter De Schrijver
2013-04-04 17:52 ` Peter De Schrijver
2013-04-04 17:52 ` Peter De Schrijver
2013-02-21 12:58 ` Prashant Gaikwad
2013-02-21 12:58 ` Prashant Gaikwad
2013-02-21 12:58 ` Prashant Gaikwad
2013-02-15 12:36 ` [PATCH v7 06/12] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 07/12] clk: tegra: Workaround for Tegra114 MSENC problem Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-18 15:40 ` [PATCH v7 00/12] Tegra114 clockframework Peter De Schrijver
2013-02-18 15:40 ` Peter De Schrijver
2013-02-18 15:40 ` Peter De Schrijver
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