From: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Grant Likely
<grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
Rob Landley <rob-VoJi6FS/r0vR7s880joybQ@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH v7 04/12] clk: tegra: Add PLL post divider table
Date: Fri, 15 Feb 2013 14:36:34 +0200 [thread overview]
Message-ID: <1360931849-7090-5-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------
drivers/clk/tegra/clk-tegra20.c | 7 +++++++
drivers/clk/tegra/clk-tegra30.c | 7 +++++++
drivers/clk/tegra/clk.h | 13 +++++++++++++
4 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 4ee6d03..08f4eb7 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -263,6 +263,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate, unsigned long parent_rate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
+ struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
unsigned long cfreq;
u32 p_div = 0;
@@ -296,7 +297,6 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->output_rate <<= 1)
p_div++;
- cfg->p = p_div;
cfg->m = parent_rate / cfreq;
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
@@ -309,8 +309,19 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
return -EINVAL;
}
- if (pll->flags & TEGRA_PLLU)
- cfg->p ^= 1;
+ if (p_tohw) {
+ p_div = 1 << p_div;
+ while (p_tohw->pdiv) {
+ if (p_div <= p_tohw->pdiv) {
+ cfg->p = p_tohw->hw_val;
+ break;
+ }
+ p_tohw++;
+ }
+ if (!p_tohw->pdiv)
+ return -EINVAL;
+ } else
+ cfg->p = p_div;
return 0;
}
@@ -457,8 +468,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
+ struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
u32 val;
u64 rate = parent_rate;
+ int pdiv;
val = pll_readl_base(pll);
@@ -477,10 +490,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
_get_pll_mnp(pll, &cfg);
- if (pll->flags & TEGRA_PLLU)
- cfg.p ^= 1;
+ if (p_tohw) {
+ while (p_tohw->pdiv) {
+ if (cfg.p == p_tohw->hw_val) {
+ pdiv = p_tohw->pdiv;
+ break;
+ }
+ p_tohw++;
+ }
+
+ if (!p_tohw->pdiv) {
+ WARN_ON(1);
+ pdiv = 1;
+ }
+ } else
+ pdiv = 1 << cfg.p;
- cfg.m *= 1 << cfg.p;
+ cfg.m *= pdiv;
rate *= cfg.n;
do_div(rate, cfg.m);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 30bd3fd..54c6777 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -440,6 +440,12 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_delay = 1000,
};
+static struct pdiv_map pllu_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 2, .hw_val = 0 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_params pll_u_params = {
.input_min = 2000000,
.input_max = 40000000,
@@ -452,6 +458,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+ .pdiv_tohw = pllu_p,
};
static struct tegra_clk_pll_params pll_x_params = {
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 28a2997..078f9b8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -466,6 +466,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
+static struct pdiv_map pllu_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 2, .hw_val = 0 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 0, 12},
{ 13000000, 480000000, 960, 13, 0, 12},
@@ -639,6 +645,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+ .pdiv_tohw = pllu_p,
};
static struct tegra_clk_pll_params pll_x_params = {
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2697aa8..79b93ee 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
};
/**
+ * struct pdiv_map - map post divider to hw value
+ *
+ * @pdiv: post divider
+ * @hw_val: value to be written to the PLL hw
+ */
+struct pdiv_map {
+ u8 pdiv;
+ u8 hw_val;
+};
+
+/**
* struct clk_pll_params - PLL parameters
*
* @input_min: Minimum input frequency
@@ -146,6 +157,8 @@ struct tegra_clk_pll_params {
u32 lock_bit_idx;
u32 lock_enable_bit_idx;
int lock_delay;
+ int max_p;
+ struct pdiv_map *pdiv_tohw;
};
/**
--
1.7.1
WARNING: multiple messages have this Message-ID (diff)
From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Grant Likely <grant.likely@secretlab.ca>,
Rob Herring <rob.herring@calxeda.com>,
Rob Landley <rob@landley.net>,
Stephen Warren <swarren@wwwdotorg.org>,
Russell King <linux@arm.linux.org.uk>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Simon Glass <sjg@chromium.org>,
Mike Turquette <mturquette@linaro.org>,
Joseph Lo <josephl@nvidia.com>,
<devicetree-discuss@lists.ozlabs.org>,
<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 04/12] clk: tegra: Add PLL post divider table
Date: Fri, 15 Feb 2013 14:36:34 +0200 [thread overview]
Message-ID: <1360931849-7090-5-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver@nvidia.com>
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------
drivers/clk/tegra/clk-tegra20.c | 7 +++++++
drivers/clk/tegra/clk-tegra30.c | 7 +++++++
drivers/clk/tegra/clk.h | 13 +++++++++++++
4 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 4ee6d03..08f4eb7 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -263,6 +263,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate, unsigned long parent_rate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
+ struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
unsigned long cfreq;
u32 p_div = 0;
@@ -296,7 +297,6 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->output_rate <<= 1)
p_div++;
- cfg->p = p_div;
cfg->m = parent_rate / cfreq;
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
@@ -309,8 +309,19 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
return -EINVAL;
}
- if (pll->flags & TEGRA_PLLU)
- cfg->p ^= 1;
+ if (p_tohw) {
+ p_div = 1 << p_div;
+ while (p_tohw->pdiv) {
+ if (p_div <= p_tohw->pdiv) {
+ cfg->p = p_tohw->hw_val;
+ break;
+ }
+ p_tohw++;
+ }
+ if (!p_tohw->pdiv)
+ return -EINVAL;
+ } else
+ cfg->p = p_div;
return 0;
}
@@ -457,8 +468,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
+ struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
u32 val;
u64 rate = parent_rate;
+ int pdiv;
val = pll_readl_base(pll);
@@ -477,10 +490,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
_get_pll_mnp(pll, &cfg);
- if (pll->flags & TEGRA_PLLU)
- cfg.p ^= 1;
+ if (p_tohw) {
+ while (p_tohw->pdiv) {
+ if (cfg.p == p_tohw->hw_val) {
+ pdiv = p_tohw->pdiv;
+ break;
+ }
+ p_tohw++;
+ }
+
+ if (!p_tohw->pdiv) {
+ WARN_ON(1);
+ pdiv = 1;
+ }
+ } else
+ pdiv = 1 << cfg.p;
- cfg.m *= 1 << cfg.p;
+ cfg.m *= pdiv;
rate *= cfg.n;
do_div(rate, cfg.m);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 30bd3fd..54c6777 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -440,6 +440,12 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_delay = 1000,
};
+static struct pdiv_map pllu_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 2, .hw_val = 0 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_params pll_u_params = {
.input_min = 2000000,
.input_max = 40000000,
@@ -452,6 +458,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+ .pdiv_tohw = pllu_p,
};
static struct tegra_clk_pll_params pll_x_params = {
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 28a2997..078f9b8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -466,6 +466,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
+static struct pdiv_map pllu_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 2, .hw_val = 0 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 0, 12},
{ 13000000, 480000000, 960, 13, 0, 12},
@@ -639,6 +645,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+ .pdiv_tohw = pllu_p,
};
static struct tegra_clk_pll_params pll_x_params = {
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2697aa8..79b93ee 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
};
/**
+ * struct pdiv_map - map post divider to hw value
+ *
+ * @pdiv: post divider
+ * @hw_val: value to be written to the PLL hw
+ */
+struct pdiv_map {
+ u8 pdiv;
+ u8 hw_val;
+};
+
+/**
* struct clk_pll_params - PLL parameters
*
* @input_min: Minimum input frequency
@@ -146,6 +157,8 @@ struct tegra_clk_pll_params {
u32 lock_bit_idx;
u32 lock_enable_bit_idx;
int lock_delay;
+ int max_p;
+ struct pdiv_map *pdiv_tohw;
};
/**
--
1.7.1
WARNING: multiple messages have this Message-ID (diff)
From: pdeschrijver@nvidia.com (Peter De Schrijver)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 04/12] clk: tegra: Add PLL post divider table
Date: Fri, 15 Feb 2013 14:36:34 +0200 [thread overview]
Message-ID: <1360931849-7090-5-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360931849-7090-1-git-send-email-pdeschrijver@nvidia.com>
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 38 ++++++++++++++++++++++++++++++++------
drivers/clk/tegra/clk-tegra20.c | 7 +++++++
drivers/clk/tegra/clk-tegra30.c | 7 +++++++
drivers/clk/tegra/clk.h | 13 +++++++++++++
4 files changed, 59 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 4ee6d03..08f4eb7 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -263,6 +263,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
unsigned long rate, unsigned long parent_rate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
+ struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
unsigned long cfreq;
u32 p_div = 0;
@@ -296,7 +297,6 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->output_rate <<= 1)
p_div++;
- cfg->p = p_div;
cfg->m = parent_rate / cfreq;
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
@@ -309,8 +309,19 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
return -EINVAL;
}
- if (pll->flags & TEGRA_PLLU)
- cfg->p ^= 1;
+ if (p_tohw) {
+ p_div = 1 << p_div;
+ while (p_tohw->pdiv) {
+ if (p_div <= p_tohw->pdiv) {
+ cfg->p = p_tohw->hw_val;
+ break;
+ }
+ p_tohw++;
+ }
+ if (!p_tohw->pdiv)
+ return -EINVAL;
+ } else
+ cfg->p = p_div;
return 0;
}
@@ -457,8 +468,10 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
+ struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
u32 val;
u64 rate = parent_rate;
+ int pdiv;
val = pll_readl_base(pll);
@@ -477,10 +490,23 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
_get_pll_mnp(pll, &cfg);
- if (pll->flags & TEGRA_PLLU)
- cfg.p ^= 1;
+ if (p_tohw) {
+ while (p_tohw->pdiv) {
+ if (cfg.p == p_tohw->hw_val) {
+ pdiv = p_tohw->pdiv;
+ break;
+ }
+ p_tohw++;
+ }
+
+ if (!p_tohw->pdiv) {
+ WARN_ON(1);
+ pdiv = 1;
+ }
+ } else
+ pdiv = 1 << cfg.p;
- cfg.m *= 1 << cfg.p;
+ cfg.m *= pdiv;
rate *= cfg.n;
do_div(rate, cfg.m);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 30bd3fd..54c6777 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -440,6 +440,12 @@ static struct tegra_clk_pll_params pll_d_params = {
.lock_delay = 1000,
};
+static struct pdiv_map pllu_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 2, .hw_val = 0 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_params pll_u_params = {
.input_min = 2000000,
.input_max = 40000000,
@@ -452,6 +458,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+ .pdiv_tohw = pllu_p,
};
static struct tegra_clk_pll_params pll_x_params = {
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 28a2997..078f9b8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -466,6 +466,12 @@ static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
{ 0, 0, 0, 0, 0, 0 },
};
+static struct pdiv_map pllu_p[] = {
+ { .pdiv = 1, .hw_val = 1 },
+ { .pdiv = 2, .hw_val = 0 },
+ { .pdiv = 0, .hw_val = 0 },
+};
+
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
{ 12000000, 480000000, 960, 12, 0, 12},
{ 13000000, 480000000, 960, 13, 0, 12},
@@ -639,6 +645,7 @@ static struct tegra_clk_pll_params pll_u_params = {
.lock_bit_idx = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
.lock_delay = 1000,
+ .pdiv_tohw = pllu_p,
};
static struct tegra_clk_pll_params pll_x_params = {
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2697aa8..79b93ee 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
};
/**
+ * struct pdiv_map - map post divider to hw value
+ *
+ * @pdiv: post divider
+ * @hw_val: value to be written to the PLL hw
+ */
+struct pdiv_map {
+ u8 pdiv;
+ u8 hw_val;
+};
+
+/**
* struct clk_pll_params - PLL parameters
*
* @input_min: Minimum input frequency
@@ -146,6 +157,8 @@ struct tegra_clk_pll_params {
u32 lock_bit_idx;
u32 lock_enable_bit_idx;
int lock_delay;
+ int max_p;
+ struct pdiv_map *pdiv_tohw;
};
/**
--
1.7.1
next prev parent reply other threads:[~2013-02-15 12:36 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-15 12:36 [PATCH v7 00/12] Tegra114 clockframework Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 01/12] clk: tegra: provide dummy cpu car ops Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
[not found] ` <1360931849-7090-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-02-15 12:36 ` [PATCH v7 02/12] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 03/12] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver [this message]
2013-02-15 12:36 ` [PATCH v7 04/12] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 05/12] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 08/12] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 09/12] clk: tegra: Implement clocks for Tegra114 Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 10/12] clk: tegra: devicetree match for nvidia, tegra114-car Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 10/12] clk: tegra: devicetree match for nvidia,tegra114-car Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 11/12] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 12/12] clk: tegra: Remove forced clk_enable of uartd Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-19 18:39 ` [PATCH v7 00/12] Tegra114 clockframework Stephen Warren
2013-02-19 18:39 ` Stephen Warren
2013-02-19 18:39 ` Stephen Warren
[not found] ` <5123C6E7.9070407-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-02-19 18:50 ` Mike Turquette
2013-02-19 18:50 ` Mike Turquette
2013-02-19 18:50 ` Mike Turquette
2013-04-04 17:52 ` Peter De Schrijver
2013-04-04 17:52 ` Peter De Schrijver
2013-04-04 17:52 ` Peter De Schrijver
2013-02-21 12:58 ` Prashant Gaikwad
2013-02-21 12:58 ` Prashant Gaikwad
2013-02-21 12:58 ` Prashant Gaikwad
2013-02-15 12:36 ` [PATCH v7 06/12] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` [PATCH v7 07/12] clk: tegra: Workaround for Tegra114 MSENC problem Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-15 12:36 ` Peter De Schrijver
2013-02-18 15:40 ` [PATCH v7 00/12] Tegra114 clockframework Peter De Schrijver
2013-02-18 15:40 ` Peter De Schrijver
2013-02-18 15:40 ` Peter De Schrijver
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