From: Nishanth Menon <nm@ti.com>
To: Tony Lindgren <tony@atomide.com>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Sricharan R <r.sricharan@ti.com>
Cc: Sekhar Nori <nsekhar@ti.com>, Rajendra Nayak <rnayak@ti.com>,
Nishanth Menon <nm@ti.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-omap@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 13/15] bus: omap_l3_noc: introduce concept of submodule
Date: Mon, 14 Apr 2014 11:25:24 -0500 [thread overview]
Message-ID: <1397492726-17203-15-git-send-email-nm@ti.com> (raw)
In-Reply-To: <1397492726-17203-1-git-send-email-nm@ti.com>
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.
To better represent this in the driver, we use the concept of submodule.
The address defintions in the devicetree is as per the high level
clock domain(module) base, the sub clockdomain/subdomain which shares
the same register space of a clockdomain is marked in the SoC data as
L3_BASE_IS_SUBMODULE.
L3_BASE_IS_SUBMODULE is used as an indication that it's base address is
the same as the parent module and offsets are considered from the same
base address as they are usually intermingled.
Other than the base address, the submodule is same as a module as it is
functionally so.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
drivers/bus/omap_l3_noc.c | 17 ++++++++++++-----
drivers/bus/omap_l3_noc.h | 6 +++++-
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 49b19d5..5e2a89d 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -184,7 +184,7 @@ static int omap_l3_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id;
static struct omap_l3 *l3;
- int ret, i;
+ int ret, i, res_idx;
of_id = of_match_device(l3_noc_match, &pdev->dev);
if (!of_id) {
@@ -201,15 +201,22 @@ static int omap_l3_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, l3);
/* Get mem resources */
- for (i = 0; i < l3->num_modules; i++) {
- struct resource *res = platform_get_resource(pdev,
- IORESOURCE_MEM, i);
-
+ for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
+ struct resource *res;
+
+ if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
+ /* First entry cannot be submodule */
+ BUG_ON(i == 0);
+ l3->l3_base[i] = l3->l3_base[i - 1];
+ continue;
+ }
+ res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(l3->l3_base[i])) {
dev_err(l3->dev, "ioremap %d failed\n", i);
return PTR_ERR(l3->l3_base[i]);
}
+ res_idx++;
}
/*
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index af33b6e..592821f 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -36,6 +36,8 @@
#define L3_TARGET_NOT_SUPPORTED NULL
+#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
+
/**
* struct l3_masters_data - L3 Master information
* @id: ID of the L3 Master
@@ -76,7 +78,9 @@ struct l3_flagmux_data {
/**
* struct omap_l3 - Description of data relevant for L3 bus.
* @dev: device representing the bus (populated runtime)
- * @l3_base: base addresses of modules (populated runtime)
+ * @l3_base: base addresses of modules (populated runtime if 0)
+ * if set to L3_BASE_IS_SUBMODULE, then uses previous
+ * module index as the base address
* @l3_flag_mux: array containing flag mux data per module
* offset from corresponding module base indexed per
* module.
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Nishanth Menon <nm@ti.com>
To: Tony Lindgren <tony@atomide.com>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Sricharan R <r.sricharan@ti.com>
Cc: Nishanth Menon <nm@ti.com>,
devicetree@vger.kernel.org, Rajendra Nayak <rnayak@ti.com>,
Sekhar Nori <nsekhar@ti.com>,
linux-kernel@vger.kernel.org,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/15] bus: omap_l3_noc: introduce concept of submodule
Date: Mon, 14 Apr 2014 11:25:24 -0500 [thread overview]
Message-ID: <1397492726-17203-15-git-send-email-nm@ti.com> (raw)
In-Reply-To: <1397492726-17203-1-git-send-email-nm@ti.com>
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.
To better represent this in the driver, we use the concept of submodule.
The address defintions in the devicetree is as per the high level
clock domain(module) base, the sub clockdomain/subdomain which shares
the same register space of a clockdomain is marked in the SoC data as
L3_BASE_IS_SUBMODULE.
L3_BASE_IS_SUBMODULE is used as an indication that it's base address is
the same as the parent module and offsets are considered from the same
base address as they are usually intermingled.
Other than the base address, the submodule is same as a module as it is
functionally so.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
drivers/bus/omap_l3_noc.c | 17 ++++++++++++-----
drivers/bus/omap_l3_noc.h | 6 +++++-
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 49b19d5..5e2a89d 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -184,7 +184,7 @@ static int omap_l3_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id;
static struct omap_l3 *l3;
- int ret, i;
+ int ret, i, res_idx;
of_id = of_match_device(l3_noc_match, &pdev->dev);
if (!of_id) {
@@ -201,15 +201,22 @@ static int omap_l3_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, l3);
/* Get mem resources */
- for (i = 0; i < l3->num_modules; i++) {
- struct resource *res = platform_get_resource(pdev,
- IORESOURCE_MEM, i);
-
+ for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
+ struct resource *res;
+
+ if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
+ /* First entry cannot be submodule */
+ BUG_ON(i == 0);
+ l3->l3_base[i] = l3->l3_base[i - 1];
+ continue;
+ }
+ res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(l3->l3_base[i])) {
dev_err(l3->dev, "ioremap %d failed\n", i);
return PTR_ERR(l3->l3_base[i]);
}
+ res_idx++;
}
/*
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index af33b6e..592821f 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -36,6 +36,8 @@
#define L3_TARGET_NOT_SUPPORTED NULL
+#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
+
/**
* struct l3_masters_data - L3 Master information
* @id: ID of the L3 Master
@@ -76,7 +78,9 @@ struct l3_flagmux_data {
/**
* struct omap_l3 - Description of data relevant for L3 bus.
* @dev: device representing the bus (populated runtime)
- * @l3_base: base addresses of modules (populated runtime)
+ * @l3_base: base addresses of modules (populated runtime if 0)
+ * if set to L3_BASE_IS_SUBMODULE, then uses previous
+ * module index as the base address
* @l3_flag_mux: array containing flag mux data per module
* offset from corresponding module base indexed per
* module.
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: nm@ti.com (Nishanth Menon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/15] bus: omap_l3_noc: introduce concept of submodule
Date: Mon, 14 Apr 2014 11:25:24 -0500 [thread overview]
Message-ID: <1397492726-17203-15-git-send-email-nm@ti.com> (raw)
In-Reply-To: <1397492726-17203-1-git-send-email-nm@ti.com>
While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2
and the first one then is internally divided into 2 sub clock domains.
To better represent this in the driver, we use the concept of submodule.
The address defintions in the devicetree is as per the high level
clock domain(module) base, the sub clockdomain/subdomain which shares
the same register space of a clockdomain is marked in the SoC data as
L3_BASE_IS_SUBMODULE.
L3_BASE_IS_SUBMODULE is used as an indication that it's base address is
the same as the parent module and offsets are considered from the same
base address as they are usually intermingled.
Other than the base address, the submodule is same as a module as it is
functionally so.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
drivers/bus/omap_l3_noc.c | 17 ++++++++++++-----
drivers/bus/omap_l3_noc.h | 6 +++++-
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 49b19d5..5e2a89d 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -184,7 +184,7 @@ static int omap_l3_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id;
static struct omap_l3 *l3;
- int ret, i;
+ int ret, i, res_idx;
of_id = of_match_device(l3_noc_match, &pdev->dev);
if (!of_id) {
@@ -201,15 +201,22 @@ static int omap_l3_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, l3);
/* Get mem resources */
- for (i = 0; i < l3->num_modules; i++) {
- struct resource *res = platform_get_resource(pdev,
- IORESOURCE_MEM, i);
-
+ for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
+ struct resource *res;
+
+ if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
+ /* First entry cannot be submodule */
+ BUG_ON(i == 0);
+ l3->l3_base[i] = l3->l3_base[i - 1];
+ continue;
+ }
+ res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(l3->l3_base[i])) {
dev_err(l3->dev, "ioremap %d failed\n", i);
return PTR_ERR(l3->l3_base[i]);
}
+ res_idx++;
}
/*
diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h
index af33b6e..592821f 100644
--- a/drivers/bus/omap_l3_noc.h
+++ b/drivers/bus/omap_l3_noc.h
@@ -36,6 +36,8 @@
#define L3_TARGET_NOT_SUPPORTED NULL
+#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
+
/**
* struct l3_masters_data - L3 Master information
* @id: ID of the L3 Master
@@ -76,7 +78,9 @@ struct l3_flagmux_data {
/**
* struct omap_l3 - Description of data relevant for L3 bus.
* @dev: device representing the bus (populated runtime)
- * @l3_base: base addresses of modules (populated runtime)
+ * @l3_base: base addresses of modules (populated runtime if 0)
+ * if set to L3_BASE_IS_SUBMODULE, then uses previous
+ * module index as the base address
* @l3_flag_mux: array containing flag mux data per module
* offset from corresponding module base indexed per
* module.
--
1.7.9.5
next prev parent reply other threads:[~2014-04-14 16:50 UTC|newest]
Thread overview: 256+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-14 16:25 [PATCH 00/15] bus: omap_l3_noc: driver cleanups and support for DRA7/AM4372 Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 01/15] bus: omap_l3_noc: Fix copyright information Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 02/15] bus: omap_l3_noc: switched over to relaxed variants of readl/writel Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:27 ` Nishanth Menon
2014-04-14 16:27 ` Nishanth Menon
2014-04-14 16:27 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 02/15] bus: omap_l3_noc: switch " Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 03/15] bus: omap_l3_noc: un-obfuscate l3_targ address computation Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 04/15] bus: omap_l3_noc: move L3 master data structure out Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 05/15] bus: omap_l3_noc: convert target information into a structure Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 06/15] bus: omap_l3_noc: make error reporting and handling common Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 07/15] bus: omap_l3_noc: populate l3->dev and use it Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 08/15] bus: omap_l3_noc: Add support for discountinous flag mux input numbers Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 09/15] bus: omap_l3_noc: rename functions and data to omap_l3 Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 10/15] bus: omap_l3_noc: remove iclk from omap_l3 struct Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 11/15] bus: omap_l3_noc: use of_match_data to pick up SoC information Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 12/15] bus: omap_l3_noc: convert flagmux information into a structure Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon [this message]
2014-04-14 16:25 ` [PATCH 13/15] bus: omap_l3_noc: introduce concept of submodule Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 14/15] bus: omap_l3_noc: Add DRA7 interconnect error data Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` [PATCH 15/15] bus: omap_l3_noc: Add AM4372 " Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-14 16:25 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 00/19] bus: omap_l3_noc: driver cleanups and support for DRA7/AM4372 Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 01/19] bus: omap_l3_noc: Fix copyright information Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:51 ` Santosh Shilimkar
2014-04-17 20:51 ` Santosh Shilimkar
2014-04-17 20:51 ` Santosh Shilimkar
2014-04-17 20:49 ` [PATCH V2 02/19] bus: omap_l3_noc: rename functions and data to omap_l3 Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:52 ` Santosh Shilimkar
2014-04-17 20:52 ` Santosh Shilimkar
2014-04-17 20:52 ` Santosh Shilimkar
2014-04-17 20:49 ` [PATCH V2 03/19] bus: omap_l3_noc: remove iclk from omap_l3 struct Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:52 ` Santosh Shilimkar
2014-04-17 20:52 ` Santosh Shilimkar
2014-04-17 20:52 ` Santosh Shilimkar
2014-04-17 20:49 ` [PATCH V2 04/19] bus: omap_l3_noc: populate l3->dev and use it Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 05/19] bus: omap_l3_noc: switch over to relaxed variants of readl/writel Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 21:52 ` Felipe Balbi
2014-04-17 21:52 ` Felipe Balbi
2014-04-17 21:52 ` Felipe Balbi
2014-04-17 21:56 ` Santosh Shilimkar
2014-04-17 21:56 ` Santosh Shilimkar
2014-04-17 21:56 ` Santosh Shilimkar
2014-04-17 22:03 ` Felipe Balbi
2014-04-17 22:03 ` Felipe Balbi
2014-04-17 22:03 ` Felipe Balbi
2014-04-21 13:16 ` Nishanth Menon
2014-04-21 13:16 ` Nishanth Menon
2014-04-21 13:16 ` Nishanth Menon
2014-04-21 15:09 ` Felipe Balbi
2014-04-21 15:09 ` Felipe Balbi
2014-04-21 15:09 ` Felipe Balbi
2014-04-21 15:31 ` Nishanth Menon
2014-04-21 15:31 ` Nishanth Menon
2014-04-21 15:31 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 06/19] bus: omap_l3_noc: un-obfuscate l3_targ address computation Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 22:00 ` Felipe Balbi
2014-04-17 22:00 ` Felipe Balbi
2014-04-17 22:00 ` Felipe Balbi
2014-04-21 13:08 ` Nishanth Menon
2014-04-21 13:08 ` Nishanth Menon
2014-04-21 13:08 ` Nishanth Menon
2014-04-21 15:11 ` Felipe Balbi
2014-04-21 15:11 ` Felipe Balbi
2014-04-21 15:11 ` Felipe Balbi
2014-04-17 20:49 ` [PATCH V2 07/19] bus: omap_l3_noc: move L3 master data structure out Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 08/19] bus: omap_l3_noc: convert target information into a structure Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 09/19] bus: omap_l3_noc: Add support for discountinous flag mux input numbers Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 10/19] bus: omap_l3_noc: use of_match_data to pick up SoC information Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 11/19] bus: omap_l3_noc: convert flagmux information into a structure Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 12/19] bus: omap_l3_noc: fix masterid detection Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 13/19] bus: omap_l3_noc: make error reporting and handling common Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 14/19] bus: omap_l3_noc: improve readability by using helper for slave event parsing Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 15/19] bus: omap_l3_noc: add information about the type of operation Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 16/19] bus: omap_l3_noc: Add information about the context " Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 17/19] bus: omap_l3_noc: introduce concept of submodule Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 18/19] bus: omap_l3_noc: Add DRA7 interconnect error data Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` [PATCH V2 19/19] bus: omap_l3_noc: Add AM4372 " Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:49 ` Nishanth Menon
2014-04-17 20:57 ` [PATCH V2 00/19] bus: omap_l3_noc: driver cleanups and support for DRA7/AM4372 Santosh Shilimkar
2014-04-17 20:57 ` Santosh Shilimkar
2014-04-17 20:57 ` Santosh Shilimkar
2014-04-17 21:00 ` Nishanth Menon
2014-04-17 21:00 ` Nishanth Menon
2014-04-17 21:00 ` Nishanth Menon
2014-04-24 8:55 ` Peter Ujfalusi
2014-04-24 8:55 ` Peter Ujfalusi
2014-04-24 8:55 ` Peter Ujfalusi
2014-04-24 14:19 ` Nishanth Menon
2014-04-24 14:19 ` Nishanth Menon
2014-04-24 14:19 ` Nishanth Menon
2014-04-25 6:27 ` Peter Ujfalusi
2014-04-25 6:27 ` Peter Ujfalusi
2014-04-25 6:27 ` Peter Ujfalusi
2014-04-25 13:44 ` Nishanth Menon
2014-04-25 13:44 ` Nishanth Menon
2014-04-25 13:44 ` Nishanth Menon
2014-04-24 16:25 ` Tony Lindgren
2014-04-24 16:25 ` Tony Lindgren
2014-04-24 16:25 ` Tony Lindgren
2014-04-24 16:31 ` Nishanth Menon
2014-04-24 16:31 ` Nishanth Menon
2014-04-24 16:31 ` Nishanth Menon
2014-04-24 15:54 ` Darren Etheridge
2014-04-24 15:54 ` Darren Etheridge
2014-04-24 15:54 ` Darren Etheridge
2014-04-24 16:06 ` Nishanth Menon
2014-04-24 16:06 ` Nishanth Menon
2014-04-24 16:06 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 00/20] " Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 01/20] bus: omap_l3_noc: Fix copyright information Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 02/20] bus: omap_l3_noc: rename functions and data to omap_l3 Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 03/20] bus: omap_l3_noc: remove iclk from omap_l3 struct Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 04/20] bus: omap_l3_noc: populate l3->dev and use it Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 05/20] bus: omap_l3_noc: switch over to relaxed variants of readl/writel Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 06/20] bus: omap_l3_noc: un-obfuscate l3_targ address computation Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 07/20] bus: omap_l3_noc: move L3 master data structure out Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 08/20] bus: omap_l3_noc: convert target information into a structure Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 09/20] bus: omap_l3_noc: Add support for discountinous flag mux input numbers Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 10/20] bus: omap_l3_noc: use of_match_data to pick up SoC information Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 11/20] bus: omap_l3_noc: convert flagmux information into a structure Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 12/20] bus: omap_l3_noc: fix masterid detection Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 13/20] bus: omap_l3_noc: make error reporting and handling common Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 14/20] bus: omap_l3_noc: improve readability by using helper for slave event parsing Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 15/20] bus: omap_l3_noc: ignore masked out unclearable targets Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 16/20] bus: omap_l3_noc: add information about the type of operation Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 17/20] bus: omap_l3_noc: Add information about the context " Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 18/20] bus: omap_l3_noc: introduce concept of submodule Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` [PATCH V3 19/20] bus: omap_l3_noc: Add DRA7 interconnect error data Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:14 ` Nishanth Menon
2014-04-28 15:15 ` [PATCH V3 20/20] bus: omap_l3_noc: Add AM4372 " Nishanth Menon
2014-04-28 15:15 ` Nishanth Menon
2014-04-28 15:15 ` Nishanth Menon
2014-04-29 13:42 ` [PATCH V3 00/20] bus: omap_l3_noc: driver cleanups and support for DRA7/AM4372 Sekhar Nori
2014-04-29 13:42 ` Sekhar Nori
2014-04-29 13:42 ` Sekhar Nori
2014-05-05 20:03 ` [GIT PULL #1/2] bus: omap_l3_noc: driver fixes and DRA7/AM437x support Nishanth Menon
2014-05-05 20:03 ` Nishanth Menon
2014-05-05 20:03 ` Nishanth Menon
2014-05-05 20:06 ` [GIT PULL #2/2] ARM: dts: DRA7/AM437x l3noc dts updates Nishanth Menon
2014-05-05 20:06 ` Nishanth Menon
2014-05-05 20:06 ` Nishanth Menon
2014-05-08 15:04 ` Tony Lindgren
2014-05-08 15:04 ` Tony Lindgren
2014-05-08 15:03 ` [GIT PULL #1/2] bus: omap_l3_noc: driver fixes and DRA7/AM437x support Tony Lindgren
2014-05-08 15:03 ` Tony Lindgren
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