From: Chen-Yu Tsai <wens@csie.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Samuel Ortiz <sameo@linux.intel.com>,
Lee Jones <lee.jones@linaro.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
Mike Turquette <mturquette@linaro.org>,
Emilio Lopez <emilio@elopez.com.ar>,
Linus Walleij <linus.walleij@linaro.org>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
Boris BREZILLON <boris.brezillon@free-electrons.com>,
Luc Verhaegen <libv@skynet.be>
Subject: [PATCH 08/22] clk: sunxi: Specify number of child clocks for divs clocks
Date: Fri, 23 May 2014 15:51:11 +0800 [thread overview]
Message-ID: <1400831485-28576-9-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org>
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.
On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.
This patch adds an entry for the number of child clocks alongside
the data structures for them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi/clk-sunxi.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6500a1b..6857c6e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -933,6 +933,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
struct divs_data {
const struct factors_data *factors; /* data for the factor clock */
+ int ndivs; /* number of children */
struct {
u8 fixed; /* is it a fixed divisor? if not... */
struct clk_div_table *table; /* is it a table based divisor? */
@@ -952,6 +953,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
static const struct divs_data pll5_divs_data __initconst = {
.factors = &sun4i_pll5_data,
+ .ndivs = 2,
.div = {
{ .shift = 0, .pow = 0, }, /* M, DDR */
{ .shift = 16, .pow = 1, }, /* P, other */
@@ -960,6 +962,7 @@ static const struct divs_data pll5_divs_data __initconst = {
static const struct divs_data pll6_divs_data __initconst = {
.factors = &sun4i_pll6_data,
+ .ndivs = 2,
.div = {
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
{ .fixed = 2 }, /* P, other */
@@ -990,7 +993,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
struct clk_fixed_factor *fix_factor;
struct clk_divider *divider;
void *reg;
- int i = 0;
+ int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
int flags, clkflags;
/* Set up factor clock that we will be dividing */
@@ -1013,7 +1016,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
* our RAM clock! */
clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
- for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+ /* if number of children known, use it */
+ if (data->ndivs)
+ ndivs = data->ndivs;
+
+ for (i = 0; i < ndivs; i++) {
if (of_property_read_string_index(node, "clock-output-names",
i, &clk_name) != 0)
break;
--
2.0.0.rc2
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens@csie.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Samuel Ortiz <sameo@linux.intel.com>,
Lee Jones <lee.jones@linaro.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Rob Herring <robh+dt@kernel.org>,
Mike Turquette <mturquette@linaro.org>,
Emilio Lopez <emilio@elopez.com.ar>,
Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org,
Boris BREZILLON <boris.brezillon@free-electrons.com>,
Luc Verhaegen <libv@skynet.be>,
linux-kernel@vger.kernel.org, Hans de Goede <hdegoede@redhat.com>,
Chen-Yu Tsai <wens@csie.org>,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 08/22] clk: sunxi: Specify number of child clocks for divs clocks
Date: Fri, 23 May 2014 15:51:11 +0800 [thread overview]
Message-ID: <1400831485-28576-9-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org>
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.
On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.
This patch adds an entry for the number of child clocks alongside
the data structures for them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi/clk-sunxi.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6500a1b..6857c6e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -933,6 +933,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
struct divs_data {
const struct factors_data *factors; /* data for the factor clock */
+ int ndivs; /* number of children */
struct {
u8 fixed; /* is it a fixed divisor? if not... */
struct clk_div_table *table; /* is it a table based divisor? */
@@ -952,6 +953,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
static const struct divs_data pll5_divs_data __initconst = {
.factors = &sun4i_pll5_data,
+ .ndivs = 2,
.div = {
{ .shift = 0, .pow = 0, }, /* M, DDR */
{ .shift = 16, .pow = 1, }, /* P, other */
@@ -960,6 +962,7 @@ static const struct divs_data pll5_divs_data __initconst = {
static const struct divs_data pll6_divs_data __initconst = {
.factors = &sun4i_pll6_data,
+ .ndivs = 2,
.div = {
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
{ .fixed = 2 }, /* P, other */
@@ -990,7 +993,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
struct clk_fixed_factor *fix_factor;
struct clk_divider *divider;
void *reg;
- int i = 0;
+ int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
int flags, clkflags;
/* Set up factor clock that we will be dividing */
@@ -1013,7 +1016,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
* our RAM clock! */
clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
- for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+ /* if number of children known, use it */
+ if (data->ndivs)
+ ndivs = data->ndivs;
+
+ for (i = 0; i < ndivs; i++) {
if (of_property_read_string_index(node, "clock-output-names",
i, &clk_name) != 0)
break;
--
2.0.0.rc2
WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 08/22] clk: sunxi: Specify number of child clocks for divs clocks
Date: Fri, 23 May 2014 15:51:11 +0800 [thread overview]
Message-ID: <1400831485-28576-9-git-send-email-wens@csie.org> (raw)
In-Reply-To: <1400831485-28576-1-git-send-email-wens@csie.org>
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.
On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.
This patch adds an entry for the number of child clocks alongside
the data structures for them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi/clk-sunxi.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 6500a1b..6857c6e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -933,6 +933,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
struct divs_data {
const struct factors_data *factors; /* data for the factor clock */
+ int ndivs; /* number of children */
struct {
u8 fixed; /* is it a fixed divisor? if not... */
struct clk_div_table *table; /* is it a table based divisor? */
@@ -952,6 +953,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
static const struct divs_data pll5_divs_data __initconst = {
.factors = &sun4i_pll5_data,
+ .ndivs = 2,
.div = {
{ .shift = 0, .pow = 0, }, /* M, DDR */
{ .shift = 16, .pow = 1, }, /* P, other */
@@ -960,6 +962,7 @@ static const struct divs_data pll5_divs_data __initconst = {
static const struct divs_data pll6_divs_data __initconst = {
.factors = &sun4i_pll6_data,
+ .ndivs = 2,
.div = {
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
{ .fixed = 2 }, /* P, other */
@@ -990,7 +993,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
struct clk_fixed_factor *fix_factor;
struct clk_divider *divider;
void *reg;
- int i = 0;
+ int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
int flags, clkflags;
/* Set up factor clock that we will be dividing */
@@ -1013,7 +1016,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
* our RAM clock! */
clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
- for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
+ /* if number of children known, use it */
+ if (data->ndivs)
+ ndivs = data->ndivs;
+
+ for (i = 0; i < ndivs; i++) {
if (of_property_read_string_index(node, "clock-output-names",
i, &clk_name) != 0)
break;
--
2.0.0.rc2
next prev parent reply other threads:[~2014-05-23 8:32 UTC|newest]
Thread overview: 153+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-23 7:51 [PATCH 00/21] ARM: sunxi: Introduce Allwinner A23 (sun8i) support Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 01/22] serial: 8250_dw: Add optional reset control support Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 8:19 ` Arnd Bergmann
2014-05-23 8:19 ` Arnd Bergmann
2014-05-23 7:51 ` [PATCH 02/22] clk: sunxi: register clock gates with clkdev Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:47 ` Maxime Ripard
2014-05-25 18:47 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 03/22] clk: sunxi: add "pll6" to sun6i protected clock list Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:48 ` Maxime Ripard
2014-05-25 18:48 ` Maxime Ripard
2014-05-26 4:47 ` Chen-Yu Tsai
2014-05-26 4:47 ` Chen-Yu Tsai
2014-05-26 4:47 ` Chen-Yu Tsai
2014-05-27 8:32 ` Maxime Ripard
2014-05-27 8:32 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 04/22] clk: sunxi: move "ahb_sdram" to " Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:51 ` Maxime Ripard
2014-05-25 18:51 ` Maxime Ripard
2014-05-26 9:43 ` Chen-Yu Tsai
2014-05-26 9:43 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 05/22] clk: sunxi: Fix gate indexing for sun6i-a31-apb0-gates Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 06/22] clk: sunxi: Support factor clocks with N multiplier factor starting from 1 Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:43 ` Maxime Ripard
2014-05-25 18:43 ` Maxime Ripard
2014-05-25 18:43 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 07/22] clk: sunxi: Fix PLL6 calculation on sun6i Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 13:09 ` Emilio López
2014-05-23 13:09 ` Emilio López
2014-05-23 13:09 ` Emilio López
2014-05-23 14:43 ` Chen-Yu Tsai
2014-05-23 14:43 ` Chen-Yu Tsai
2014-05-23 14:43 ` Chen-Yu Tsai
2014-05-25 18:43 ` Maxime Ripard
2014-05-25 18:43 ` Maxime Ripard
2014-05-23 7:51 ` Chen-Yu Tsai [this message]
2014-05-23 7:51 ` [PATCH 08/22] clk: sunxi: Specify number of child clocks for divs clocks Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:56 ` Maxime Ripard
2014-05-25 18:56 ` Maxime Ripard
2014-05-25 18:56 ` Maxime Ripard
2014-05-26 3:47 ` Chen-Yu Tsai
2014-05-26 3:47 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 10/22] clk: sunxi: Add support for PLL6 pre-divider on AHB1 clock Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:02 ` Maxime Ripard
2014-05-25 19:02 ` Maxime Ripard
2014-05-25 19:02 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 11/22] ARM: sun6i: DT: Add PLL6 multiple outputs Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:59 ` Maxime Ripard
2014-05-25 18:59 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 12/22] ARM: sun6i: DT: Add PLL6 pre-divider clock for AHB1 mux input Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 13/22] clk: sunxi: Add A23 clocks support Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:05 ` Maxime Ripard
2014-05-25 19:05 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 14/22] clk: sunxi: Add A23 APB0 support to sun6i-a31-apb0-clk Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 15/22] pinctrl: sunxi: Add A23 PIO controller support Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:08 ` Maxime Ripard
2014-05-25 19:08 ` Maxime Ripard
2014-06-17 10:25 ` Chen-Yu Tsai
2014-06-17 10:25 ` Chen-Yu Tsai
2014-06-17 10:25 ` Chen-Yu Tsai
2014-06-17 14:18 ` Maxime Ripard
2014-06-17 14:18 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 16/22] pinctrl: sunxi: Add A23 R_PIO " Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:11 ` Maxime Ripard
2014-05-25 19:11 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 17/22] mfd: sun6i-prcm: Add support for Allwinner A23 PRCM Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:14 ` Maxime Ripard
2014-05-25 19:14 ` Maxime Ripard
2014-05-26 4:36 ` Chen-Yu Tsai
2014-05-26 4:36 ` Chen-Yu Tsai
2014-05-27 8:30 ` Maxime Ripard
2014-05-27 8:30 ` Maxime Ripard
2014-05-29 4:23 ` Chen-Yu Tsai
2014-05-29 4:23 ` Chen-Yu Tsai
2014-05-29 19:31 ` Maxime Ripard
2014-05-29 19:31 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 18/22] ARM: sunxi: Introduce Allwinner A23 support Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:22 ` Maxime Ripard
2014-05-25 19:22 ` Maxime Ripard
2014-05-25 19:22 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 19/22] ARM: sunxi: Add earlyprintk support using R_UART (sun6i/sun8i) Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 18:46 ` Maxime Ripard
2014-05-25 18:46 ` Maxime Ripard
2014-05-26 9:25 ` Chen-Yu Tsai
2014-05-26 9:25 ` Chen-Yu Tsai
2014-05-27 8:34 ` Maxime Ripard
2014-05-27 8:34 ` Maxime Ripard
2014-05-23 7:51 ` [PATCH 20/22] ARM: sun8i: Add SMP support for the Allwinner A23 Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:26 ` Maxime Ripard
2014-05-25 19:26 ` Maxime Ripard
2014-05-26 3:57 ` Chen-Yu Tsai
2014-05-26 3:57 ` Chen-Yu Tsai
2014-05-27 8:09 ` Marc Zyngier
2014-05-27 8:09 ` Marc Zyngier
2014-05-27 8:09 ` Marc Zyngier
2014-05-23 7:51 ` [PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:38 ` Maxime Ripard
2014-05-25 19:38 ` Maxime Ripard
2014-05-26 4:02 ` Chen-Yu Tsai
2014-05-26 4:02 ` Chen-Yu Tsai
2014-05-23 7:51 ` [PATCH 22/22] ARM: sun8i: dt: Add Ippo-q8h v5 support Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-23 7:51 ` Chen-Yu Tsai
2014-05-25 19:39 ` Maxime Ripard
2014-05-25 19:39 ` Maxime Ripard
2014-05-26 4:23 ` Chen-Yu Tsai
2014-05-26 4:23 ` Chen-Yu Tsai
2014-05-26 4:23 ` Chen-Yu Tsai
2014-05-27 8:22 ` Maxime Ripard
2014-05-27 8:22 ` Maxime Ripard
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