From: Kever Yang <kever.yang@rock-chips.com>
To: heiko@sntech.de, Mike Turquette <mturquette@linaro.org>
Cc: dianders@chromium.org, sonnyrao@chromium.org,
addy.ke@rock-chips.com, cf@rock-chips.com, xjq@rock-chips.com,
hj@rock-chips.com, huangtao@rock-chips.com, dkl@rock-chips.com,
Kever Yang <kever.yang@rock-chips.com>,
Russell King <linux@arm.linux.org.uk>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Kumar Gala <galak@codeaurora.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
linux-rockchip@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/2] init some clock rate from dts for rk3288
Date: Thu, 9 Oct 2014 21:50:28 -0700 [thread overview]
Message-ID: <1412916630-8256-1-git-send-email-kever.yang@rock-chips.com> (raw)
This patch add init rate for PLLs and some bus clock from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
We need Doug's patch to make "aclk_cpu" get set properly:
<https://patchwork.kernel.org/patch/5038781/>
Changes in v2:
- change the PLL setting of 400M to meet the constraints of TRM
- add review and test tag
- add some explanation in commit message
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++
drivers/clk/rockchip/clk-rk3288.c | 2 ++
2 files changed, 12 insertions(+)
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
sonnyrao-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
cf-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
xjq-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
hj-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
dkl-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Kever Yang <kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [PATCH v2 0/2] init some clock rate from dts for rk3288
Date: Thu, 9 Oct 2014 21:50:28 -0700 [thread overview]
Message-ID: <1412916630-8256-1-git-send-email-kever.yang@rock-chips.com> (raw)
This patch add init rate for PLLs and some bus clock from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
We need Doug's patch to make "aclk_cpu" get set properly:
<https://patchwork.kernel.org/patch/5038781/>
Changes in v2:
- change the PLL setting of 400M to meet the constraints of TRM
- add review and test tag
- add some explanation in commit message
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++
drivers/clk/rockchip/clk-rk3288.c | 2 ++
2 files changed, 12 insertions(+)
--
1.9.1
--
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WARNING: multiple messages have this Message-ID (diff)
From: kever.yang@rock-chips.com (Kever Yang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/2] init some clock rate from dts for rk3288
Date: Thu, 9 Oct 2014 21:50:28 -0700 [thread overview]
Message-ID: <1412916630-8256-1-git-send-email-kever.yang@rock-chips.com> (raw)
This patch add init rate for PLLs and some bus clock from dts for rk3288,
add two clock rate of 400M and 500M into rate table for we will use it.
We need Doug's patch to make "aclk_cpu" get set properly:
<https://patchwork.kernel.org/patch/5038781/>
Changes in v2:
- change the PLL setting of 400M to meet the constraints of TRM
- add review and test tag
- add some explanation in commit message
Kever Yang (2):
clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
ARM: dts: enable init rate for clock
arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++
drivers/clk/rockchip/clk-rk3288.c | 2 ++
2 files changed, 12 insertions(+)
--
1.9.1
next reply other threads:[~2014-10-10 4:50 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-10 4:50 Kever Yang [this message]
2014-10-10 4:50 ` [PATCH v2 0/2] init some clock rate from dts for rk3288 Kever Yang
2014-10-10 4:50 ` Kever Yang
2014-10-10 4:50 ` [PATCH v2 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate Kever Yang
2014-10-10 4:50 ` Kever Yang
2014-10-10 16:53 ` Doug Anderson
2014-10-10 16:53 ` Doug Anderson
2014-10-10 4:50 ` [PATCH v2 2/2] ARM: dts: enable init rate for clock Kever Yang
2014-10-10 4:50 ` Kever Yang
2014-10-16 20:22 ` [PATCH v2 0/2] init some clock rate from dts for rk3288 Heiko Stübner
2014-10-16 20:22 ` Heiko Stübner
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