From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org,
marc.zyngier@arm.com, "Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>
Subject: [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists
Date: Mon, 23 Mar 2015 17:05:44 +0000 [thread overview]
Message-ID: <1427130344-27986-7-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org>
I was getting very confused about the duplication of state so wanted to
make it explicit.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211c..6dc1799 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
uint32_t uncached_cpsr;
+ /* The spsr is a alias for spsr_elN where N is the current
+ * exception level. It is provided for here so the TCG msr/mrs
+ * implementation can access one register. Care needs to be taken
+ * to ensure the banked_spsr[] is also updated.
+ */
uint32_t spsr;
/* Banked registers. */
--
2.3.2
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
kvm@vger.kernel.org, marc.zyngier@arm.com,
linux-arm-kernel@lists.infradead.org,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org
Subject: [Qemu-devel] [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists
Date: Mon, 23 Mar 2015 17:05:44 +0000 [thread overview]
Message-ID: <1427130344-27986-7-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org>
I was getting very confused about the duplication of state so wanted to
make it explicit.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211c..6dc1799 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
uint32_t uncached_cpsr;
+ /* The spsr is a alias for spsr_elN where N is the current
+ * exception level. It is provided for here so the TCG msr/mrs
+ * implementation can access one register. Care needs to be taken
+ * to ensure the banked_spsr[] is also updated.
+ */
uint32_t spsr;
/* Banked registers. */
--
2.3.2
WARNING: multiple messages have this Message-ID (diff)
From: alex.bennee@linaro.org (Alex Bennée)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists
Date: Mon, 23 Mar 2015 17:05:44 +0000 [thread overview]
Message-ID: <1427130344-27986-7-git-send-email-alex.bennee@linaro.org> (raw)
In-Reply-To: <1427130344-27986-1-git-send-email-alex.bennee@linaro.org>
I was getting very confused about the duplication of state so wanted to
make it explicit.
Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211c..6dc1799 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
uint32_t uncached_cpsr;
+ /* The spsr is a alias for spsr_elN where N is the current
+ * exception level. It is provided for here so the TCG msr/mrs
+ * implementation can access one register. Care needs to be taken
+ * to ensure the banked_spsr[] is also updated.
+ */
uint32_t spsr;
/* Banked registers. */
--
2.3.2
next prev parent reply other threads:[~2015-03-23 17:05 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-23 17:05 [PATCH v5 0/6] QEMU ARM64 Migration Fixes Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-23 17:05 ` [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-24 14:32 ` Greg Bellows
2015-03-24 14:32 ` Greg Bellows
2015-03-24 14:32 ` Greg Bellows
2015-03-24 14:37 ` Peter Maydell
2015-03-24 14:37 ` Peter Maydell
2015-03-24 14:37 ` Peter Maydell
2015-03-23 17:05 ` [PATCH v5 2/6] target-arm: kvm: save/restore mp state Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-26 17:11 ` Peter Maydell
2015-03-26 17:11 ` Peter Maydell
2015-03-26 17:11 ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-26 17:12 ` Peter Maydell
2015-03-26 17:12 ` Peter Maydell
2015-03-26 17:12 ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` [PATCH v5 4/6] target-arm: kvm64 sync FP register state Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-26 17:20 ` Peter Maydell
2015-03-26 17:20 ` Peter Maydell
2015-03-26 17:20 ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` [PATCH v5 5/6] target-arm: kvm64 fix save/restore of SPSR regs Alex Bennée
2015-03-23 17:05 ` Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-26 17:25 ` Peter Maydell
2015-03-26 17:25 ` Peter Maydell
2015-03-26 17:25 ` [Qemu-devel] " Peter Maydell
2015-03-23 17:05 ` Alex Bennée [this message]
2015-03-23 17:05 ` [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists Alex Bennée
2015-03-23 17:05 ` [Qemu-devel] " Alex Bennée
2015-03-26 17:26 ` Peter Maydell
2015-03-26 17:26 ` Peter Maydell
2015-03-26 17:26 ` [Qemu-devel] " Peter Maydell
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