Re: [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists

From: Peter Maydell <peter.maydell@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	kvm-devel <kvm@vger.kernel.org>,
	arm-mail-list <linux-arm-kernel@lists.infradead.org>,
	"kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
	Christoffer Dall <christoffer.dall@linaro.org>,
	Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists
Date: Thu, 26 Mar 2015 17:26:32 +0000	[thread overview]
Message-ID: <CAFEAcA_x5SGWcB1qgUKCTO+6SXVh9m1PXhHmwOzYOsVz9fK_sg@mail.gmail.com> (raw)
In-Reply-To: <1427130344-27986-7-git-send-email-alex.bennee@linaro.org>

On 23 March 2015 at 17:05, Alex Bennée <alex.bennee@linaro.org> wrote:
> I was getting very confused about the duplication of state so wanted to
> make it explicit.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 083211c..6dc1799 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -155,6 +155,11 @@ typedef struct CPUARMState {
>         This contains all the other bits.  Use cpsr_{read,write} to access
>         the whole CPSR.  */
>      uint32_t uncached_cpsr;
> +    /* The spsr is a alias for spsr_elN where N is the current
> +     * exception level.

This comment is still wrong.

> It is provided for here so the TCG msr/mrs
> +     * implementation can access one register.

...and this is wrong too.

> Care needs to be taken
> +     * to ensure the banked_spsr[] is also updated.
> +     */
>      uint32_t spsr;
>
>      /* Banked registers.  */

I think it would be better to just drop this patch, really...

-- PMM