From: Mikko Perttunen <mikko.perttunen@kapsi.fi> To: swarren@wwwdotorg.org, thierry.reding@gmail.com, gnurou@gmail.com, pdeschrijver@nvidia.com, rjw@rjwysocki.net, viresh.kumar@linaro.org Cc: mturquette@linaro.org, pwalmsley@nvidia.com, vinceh@nvidia.com, pgaikwad@nvidia.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tuomas.tynkkynen@iki.fi, Tuomas Tynkkynen <ttynkkynen@nvidia.com>, Mikko Perttunen <mikko.perttunen@kapsi.fi> Subject: [PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree Date: Wed, 13 May 2015 17:58:44 +0300 [thread overview] Message-ID: <1431529131-16710-11-git-send-email-mikko.perttunen@kapsi.fi> (raw) In-Reply-To: <1431529131-16710-1-git-send-email-mikko.perttunen@kapsi.fi> From: Tuomas Tynkkynen <ttynkkynen@nvidia.com> The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> --- arch/arm/boot/dts/tegra124.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 01a9f74..5b8177a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/tegra124-car.h> #include <dt-bindings/thermal/tegra124-soctherm.h> #include "skeleton.dtsi" @@ -702,6 +703,30 @@ #thermal-sensor-cells = <1>; }; + dfll: clock@0,70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, -- 2.3.0
WARNING: multiple messages have this Message-ID (diff)
From: mikko.perttunen@kapsi.fi (Mikko Perttunen) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree Date: Wed, 13 May 2015 17:58:44 +0300 [thread overview] Message-ID: <1431529131-16710-11-git-send-email-mikko.perttunen@kapsi.fi> (raw) In-Reply-To: <1431529131-16710-1-git-send-email-mikko.perttunen@kapsi.fi> From: Tuomas Tynkkynen <ttynkkynen@nvidia.com> The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> --- arch/arm/boot/dts/tegra124.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 01a9f74..5b8177a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/tegra124-car.h> #include <dt-bindings/thermal/tegra124-soctherm.h> #include "skeleton.dtsi" @@ -702,6 +703,30 @@ #thermal-sensor-cells = <1>; }; + dfll: clock at 0,70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + ahub at 0,70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, -- 2.3.0
next prev parent reply other threads:[~2015-05-13 14:58 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-05-13 14:58 [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 01/17] clk: tegra: Add binding for the Tegra124 DFLL clocksource Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 02/17] clk: tegra: Add library for the DFLL clock source (open-loop mode) Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-19 11:39 ` [PATCH v10 " Mikko Perttunen 2015-05-19 11:39 ` Mikko Perttunen [not found] ` <1432035567-19008-1-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-19 11:46 ` Mikko Perttunen 2015-05-19 11:46 ` Mikko Perttunen 2015-05-19 11:46 ` Mikko Perttunen 2015-05-19 14:59 ` Thierry Reding 2015-05-19 14:59 ` Thierry Reding 2015-05-19 15:06 ` Mikko Perttunen 2015-05-19 15:06 ` Mikko Perttunen 2015-05-19 15:06 ` Mikko Perttunen 2015-05-19 15:22 ` Thierry Reding 2015-05-19 15:22 ` Thierry Reding 2015-05-20 6:27 ` [PATCH v11 " Mikko Perttunen 2015-05-20 6:27 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 07/17] clk: tegra: Add Tegra124 DFLL clocksource platform driver Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen [not found] ` <1431529131-16710-8-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-26 18:17 ` Kevin Hilman 2015-05-26 18:17 ` Kevin Hilman 2015-05-26 18:17 ` Kevin Hilman [not found] ` <1431529131-16710-1-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-13 14:58 ` [PATCH v9 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen [not found] ` <1431529131-16710-7-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-19 11:43 ` [PATCH v10 " Mikko Perttunen 2015-05-19 11:43 ` Mikko Perttunen 2015-05-19 11:43 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 09/17] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen [this message] 2015-05-13 14:58 ` [PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 12/17] cpufreq: tegra124: Add device tree bindings Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 14/17] cpufreq: Add cpufreq driver for Tegra124 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 15/17] ARM: tegra: Add entries for cpufreq on Tegra124 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 16/17] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 22:47 ` [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Rafael J. Wysocki 2015-05-13 22:47 ` Rafael J. Wysocki 2015-05-14 6:15 ` Mikko Perttunen 2015-05-14 6:15 ` Mikko Perttunen 2015-05-14 20:15 ` Rafael J. Wysocki 2015-05-14 20:15 ` Rafael J. Wysocki 2015-05-15 2:09 ` Viresh Kumar 2015-05-15 2:09 ` Viresh Kumar 2015-05-15 2:09 ` Viresh Kumar 2015-05-15 5:16 ` Mikko Perttunen 2015-05-15 5:16 ` Mikko Perttunen 2015-05-15 5:16 ` Mikko Perttunen
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