From: Mikko Perttunen <mikko.perttunen@kapsi.fi> To: swarren@wwwdotorg.org, thierry.reding@gmail.com, gnurou@gmail.com, pdeschrijver@nvidia.com, rjw@rjwysocki.net, viresh.kumar@linaro.org Cc: mturquette@linaro.org, pwalmsley@nvidia.com, vinceh@nvidia.com, pgaikwad@nvidia.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tuomas.tynkkynen@iki.fi, Tuomas Tynkkynen <ttynkkynen@nvidia.com>, Mikko Perttunen <mikko.perttunen@kapsi.fi> Subject: [PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1 Date: Wed, 13 May 2015 17:58:45 +0300 [thread overview] Message-ID: <1431529131-16710-12-git-send-email-mikko.perttunen@kapsi.fi> (raw) In-Reply-To: <1431529131-16710-1-git-send-email-mikko.perttunen@kapsi.fi> From: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index bd43ed6..192111a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1462,7 +1462,7 @@ vin-ldo9-10-supply = <&vdd_5v0_sys>; vin-ldo11-supply = <&vdd_3v3_run>; - sd0 { + vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; @@ -1694,6 +1694,13 @@ non-removable; }; + /* CPU DFLL clock */ + clock@0,70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + ahub@0,70300000 { i2s@0,70301100 { status = "okay"; -- 2.3.0
WARNING: multiple messages have this Message-ID (diff)
From: mikko.perttunen@kapsi.fi (Mikko Perttunen) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1 Date: Wed, 13 May 2015 17:58:45 +0300 [thread overview] Message-ID: <1431529131-16710-12-git-send-email-mikko.perttunen@kapsi.fi> (raw) In-Reply-To: <1431529131-16710-1-git-send-email-mikko.perttunen@kapsi.fi> From: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index bd43ed6..192111a 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1462,7 +1462,7 @@ vin-ldo9-10-supply = <&vdd_5v0_sys>; vin-ldo11-supply = <&vdd_3v3_run>; - sd0 { + vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; @@ -1694,6 +1694,13 @@ non-removable; }; + /* CPU DFLL clock */ + clock at 0,70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + ahub at 0,70300000 { i2s at 0,70301100 { status = "okay"; -- 2.3.0
next prev parent reply other threads:[~2015-05-13 14:58 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-05-13 14:58 [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 01/17] clk: tegra: Add binding for the Tegra124 DFLL clocksource Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 02/17] clk: tegra: Add library for the DFLL clock source (open-loop mode) Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-19 11:39 ` [PATCH v10 " Mikko Perttunen 2015-05-19 11:39 ` Mikko Perttunen [not found] ` <1432035567-19008-1-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-19 11:46 ` Mikko Perttunen 2015-05-19 11:46 ` Mikko Perttunen 2015-05-19 11:46 ` Mikko Perttunen 2015-05-19 14:59 ` Thierry Reding 2015-05-19 14:59 ` Thierry Reding 2015-05-19 15:06 ` Mikko Perttunen 2015-05-19 15:06 ` Mikko Perttunen 2015-05-19 15:06 ` Mikko Perttunen 2015-05-19 15:22 ` Thierry Reding 2015-05-19 15:22 ` Thierry Reding 2015-05-20 6:27 ` [PATCH v11 " Mikko Perttunen 2015-05-20 6:27 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 07/17] clk: tegra: Add Tegra124 DFLL clocksource platform driver Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen [not found] ` <1431529131-16710-8-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-26 18:17 ` Kevin Hilman 2015-05-26 18:17 ` Kevin Hilman 2015-05-26 18:17 ` Kevin Hilman [not found] ` <1431529131-16710-1-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-13 14:58 ` [PATCH v9 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen [not found] ` <1431529131-16710-7-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org> 2015-05-19 11:43 ` [PATCH v10 " Mikko Perttunen 2015-05-19 11:43 ` Mikko Perttunen 2015-05-19 11:43 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 09/17] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen [this message] 2015-05-13 14:58 ` [PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1 Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 12/17] cpufreq: tegra124: Add device tree bindings Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 14/17] cpufreq: Add cpufreq driver for Tegra124 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 15/17] ARM: tegra: Add entries for cpufreq on Tegra124 Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 14:58 ` [PATCH v9 16/17] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Mikko Perttunen 2015-05-13 14:58 ` Mikko Perttunen 2015-05-13 22:47 ` [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Rafael J. Wysocki 2015-05-13 22:47 ` Rafael J. Wysocki 2015-05-14 6:15 ` Mikko Perttunen 2015-05-14 6:15 ` Mikko Perttunen 2015-05-14 20:15 ` Rafael J. Wysocki 2015-05-14 20:15 ` Rafael J. Wysocki 2015-05-15 2:09 ` Viresh Kumar 2015-05-15 2:09 ` Viresh Kumar 2015-05-15 2:09 ` Viresh Kumar 2015-05-15 5:16 ` Mikko Perttunen 2015-05-15 5:16 ` Mikko Perttunen 2015-05-15 5:16 ` Mikko Perttunen
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1431529131-16710-12-git-send-email-mikko.perttunen@kapsi.fi \ --to=mikko.perttunen@kapsi.fi \ --cc=gnurou@gmail.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pm@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=mturquette@linaro.org \ --cc=pdeschrijver@nvidia.com \ --cc=pgaikwad@nvidia.com \ --cc=pwalmsley@nvidia.com \ --cc=rjw@rjwysocki.net \ --cc=swarren@wwwdotorg.org \ --cc=thierry.reding@gmail.com \ --cc=ttynkkynen@nvidia.com \ --cc=tuomas.tynkkynen@iki.fi \ --cc=vinceh@nvidia.com \ --cc=viresh.kumar@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.