From: Christoffer Dall <christoffer.dall@linaro.org> To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Marc Zyngier <marc.zyngier@arm.com>, Andre Przywara <andre.przywara@arm.com> Subject: [PATCH v3 4/8] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs Date: Tue, 29 Sep 2015 16:49:01 +0200 [thread overview] Message-ID: <1443538145-11990-5-git-send-email-christoffer.dall@linaro.org> (raw) In-Reply-To: <1443538145-11990-1-git-send-email-christoffer.dall@linaro.org> The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the reset value to the register. This is a bit counter-intuitive, as the register is RO for these bits, and we can just implement it that way, allowing us to control the value of the bits purely in the reset code. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> --- virt/kvm/arm/vgic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index fe0e5db..e606f78 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -655,7 +655,7 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (mmio->is_write) { if (offset < 8) { - *reg = ~0U; /* Force PPIs/SGIs to 1 */ + /* Ignore writes to read-only SGI and PPI bits */ return false; } -- 2.1.2.330.g565301e.dirty
WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/8] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs Date: Tue, 29 Sep 2015 16:49:01 +0200 [thread overview] Message-ID: <1443538145-11990-5-git-send-email-christoffer.dall@linaro.org> (raw) In-Reply-To: <1443538145-11990-1-git-send-email-christoffer.dall@linaro.org> The GICD_ICFGR allows the bits for the SGIs and PPIs to be read only. We currently simulate this behavior by writing a hardcoded value to the register for the SGIs and PPIs on every write of these bits to the register (ignoring what the guest actually wrote), and by writing the same value as the reset value to the register. This is a bit counter-intuitive, as the register is RO for these bits, and we can just implement it that way, allowing us to control the value of the bits purely in the reset code. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> --- virt/kvm/arm/vgic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index fe0e5db..e606f78 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -655,7 +655,7 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (mmio->is_write) { if (offset < 8) { - *reg = ~0U; /* Force PPIs/SGIs to 1 */ + /* Ignore writes to read-only SGI and PPI bits */ return false; } -- 2.1.2.330.g565301e.dirty
next prev parent reply other threads:[~2015-09-29 14:49 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-09-29 14:48 [PATCH v3 0/8] Rework architected timer and forwarded IRQs handling Christoffer Dall 2015-09-29 14:48 ` Christoffer Dall 2015-09-29 14:48 ` [PATCH v3 1/8] KVM: Add kvm_arch_vcpu_{un}blocking callbacks Christoffer Dall 2015-09-29 14:48 ` Christoffer Dall 2015-09-29 14:48 ` [PATCH v3 2/8] arm/arm64: KVM: arch_timer: Only schedule soft timer on vcpu_block Christoffer Dall 2015-09-29 14:48 ` Christoffer Dall 2015-09-29 14:49 ` [PATCH v3 3/8] arm/arm64: KVM: vgic: Factor out level irq processing on guest exit Christoffer Dall 2015-09-29 14:49 ` Christoffer Dall 2015-10-02 14:52 ` Andre Przywara 2015-10-02 14:52 ` Andre Przywara 2015-10-02 20:48 ` Christoffer Dall 2015-10-02 20:48 ` Christoffer Dall 2015-09-29 14:49 ` Christoffer Dall [this message] 2015-09-29 14:49 ` [PATCH v3 4/8] arm/arm64: KVM: Implement GICD_ICFGR as RO for PPIs Christoffer Dall 2015-10-02 14:51 ` Andre Przywara 2015-10-02 14:51 ` Andre Przywara 2015-10-02 20:52 ` Christoffer Dall 2015-10-02 20:52 ` Christoffer Dall 2015-09-29 14:49 ` [PATCH v3 5/8] arm/arm64: KVM: Use appropriate define in VGIC reset code Christoffer Dall 2015-09-29 14:49 ` Christoffer Dall 2015-10-02 14:51 ` Andre Przywara 2015-10-02 14:51 ` Andre Przywara 2015-09-29 14:49 ` [PATCH v3 6/8] arm/arm64: KVM: Add forwarded physical interrupts documentation Christoffer Dall 2015-09-29 14:49 ` Christoffer Dall 2015-09-29 14:49 ` [PATCH v3 7/8] arm/arm64: KVM: Rework the arch timer to use level-triggered semantics Christoffer Dall 2015-09-29 14:49 ` Christoffer Dall 2015-09-29 14:49 ` [PATCH v3 8/8] arm/arm64: KVM: Support edge-triggered forwarded interrupts Christoffer Dall 2015-09-29 14:49 ` Christoffer Dall 2015-10-02 17:18 ` Andre Przywara 2015-10-02 17:18 ` Andre Przywara 2015-10-02 21:08 ` Christoffer Dall 2015-10-02 21:08 ` Christoffer Dall
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