From: Yakir Yang <ykk@rock-chips.com> To: Inki Dae <inki.dae@samsung.com>, Mark Yao <mark.yao@rock-chips.com>, Jingoo Han <jingoohan1@gmail.com>, Heiko Stuebner <heiko@sntech.de> Cc: Thierry Reding <treding@nvidia.com>, Krzysztof Kozlowski <k.kozlowski@samsung.com>, Rob Herring <robh+dt@kernel.org>, Russell King <linux@arm.linux.org.uk>, emil.l.velikov@gmail.com, Gustavo Padovan <gustavo.padovan@collabora.co.uk>, Kishon Vijay Abraham I <kishon@ti.com>, javier@osg.samsung.com, Andy Yan <andy.yan@rock-chips.com>, Yakir Yang <ykk@rock-chips.com>, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v12 09/18] phy: Add driver for rockchip Display Port PHY Date: Wed, 23 Dec 2015 20:36:23 +0800 [thread overview] Message-ID: <1450874183-19261-1-git-send-email-ykk@rock-chips.com> (raw) In-Reply-To: <1450873538-18304-1-git-send-email-ykk@rock-chips.com> Add phy driver for the Rockchip DisplayPort PHY module. This is required to get DisplayPort working in Rockchip SoCs. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v12: - Re-order the include headers file alphabetically in phy-rockchip-dp.c (Jingoo) Changes in v11: None Changes in v10: - Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4) -> BIT(20) Changes in v9: - Removed the unused the variable "res" in probe function. (Heiko) - Removed the unused head file. Changes in v8: - Fix the mixed spacers on macro definitions. (Heiko) - Remove the unnecessary empty line after clk_prepare_enable. (Heiko) Changes in v7: - Simply the commit message. (Kishon) - Symmetrical enable/disbale the phy clock and power. (Kishon) Changes in v6: None Changes in v5: - Remove "reg" DT property, cause driver could poweron/poweroff phy via the exist "grf" syscon already. And rename the example DT node from "edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko) - Add deivce_node at the front of driver, update phy_ops type from "static struct" to "static const struct". And correct the input paramters of devm_phy_create() interfaces. (Heiko) Changes in v4: - Add commit message, and remove the redundant rockchip_dp_phy_init() function, move those code to probe() method. And remove driver .owner number. (Kishon) Changes in v3: - Suggest, add rockchip dp phy driver, collect the phy clocks and power control. (Heiko) Changes in v2: None drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/phy/phy-rockchip-dp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 7eb5859d..7355819 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB help Enable this to support the Rockchip USB 2.0 PHY. +config PHY_ROCKCHIP_DP + tristate "Rockchip Display Port PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip Display Port PHY. + config PHY_ST_SPEAR1310_MIPHY tristate "ST SPEAR1310-MIPHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 075db1a..b1700cd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c new file mode 100644 index 0000000..88f09ec --- /dev/null +++ b/drivers/phy/phy-rockchip-dp.c @@ -0,0 +1,151 @@ +/* + * Rockchip DP PHY driver + * + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd. + * Author: Yakir Yang <ykk@@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + */ + +#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define GRF_SOC_CON12 0x0274 + +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20) +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4) + +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21) +#define GRF_EDP_PHY_SIDDQ_ON 0 +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5) + +struct rockchip_dp_phy { + struct device *dev; + struct regmap *grf; + struct clk *phy_24m; +}; + +static int rockchip_set_phy_state(struct phy *phy, bool enable) +{ + struct rockchip_dp_phy *dp = phy_get_drvdata(phy); + int ret; + + if (enable) { + ret = regmap_write(dp->grf, GRF_SOC_CON12, + GRF_EDP_PHY_SIDDQ_HIWORD_MASK | + GRF_EDP_PHY_SIDDQ_ON); + if (ret < 0) { + dev_err(dp->dev, "Can't enable PHY power %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(dp->phy_24m); + } else { + clk_disable_unprepare(dp->phy_24m); + + ret = regmap_write(dp->grf, GRF_SOC_CON12, + GRF_EDP_PHY_SIDDQ_HIWORD_MASK | + GRF_EDP_PHY_SIDDQ_OFF); + } + + return ret; +} + +static int rockchip_dp_phy_power_on(struct phy *phy) +{ + return rockchip_set_phy_state(phy, true); +} + +static int rockchip_dp_phy_power_off(struct phy *phy) +{ + return rockchip_set_phy_state(phy, false); +} + +static const struct phy_ops rockchip_dp_phy_ops = { + .power_on = rockchip_dp_phy_power_on, + .power_off = rockchip_dp_phy_power_off, + .owner = THIS_MODULE, +}; + +static int rockchip_dp_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct phy_provider *phy_provider; + struct rockchip_dp_phy *dp; + struct phy *phy; + int ret; + + if (!np) + return -ENODEV; + + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); + if (IS_ERR(dp)) + return -ENOMEM; + + dp->dev = dev; + + dp->phy_24m = devm_clk_get(dev, "24m"); + if (IS_ERR(dp->phy_24m)) { + dev_err(dev, "cannot get clock 24m\n"); + return PTR_ERR(dp->phy_24m); + } + + ret = clk_set_rate(dp->phy_24m, 24000000); + if (ret < 0) { + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret); + return ret; + } + + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(dp->grf)) { + dev_err(dev, "rk3288-dp needs rockchip,grf property\n"); + return PTR_ERR(dp->grf); + } + + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER | + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK); + if (ret != 0) { + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret); + return ret; + } + + phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy\n"); + return PTR_ERR(phy); + } + phy_set_drvdata(phy, dp); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_dp_phy_dt_ids[] = { + { .compatible = "rockchip,rk3288-dp-phy" }, + {} +}; + +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids); + +static struct platform_driver rockchip_dp_phy_driver = { + .probe = rockchip_dp_phy_probe, + .driver = { + .name = "rockchip-dp-phy", + .of_match_table = rockchip_dp_phy_dt_ids, + }, +}; + +module_platform_driver(rockchip_dp_phy_driver); + +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); +MODULE_DESCRIPTION("Rockchip DP PHY driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: ykk@rock-chips.com (Yakir Yang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v12 09/18] phy: Add driver for rockchip Display Port PHY Date: Wed, 23 Dec 2015 20:36:23 +0800 [thread overview] Message-ID: <1450874183-19261-1-git-send-email-ykk@rock-chips.com> (raw) In-Reply-To: <1450873538-18304-1-git-send-email-ykk@rock-chips.com> Add phy driver for the Rockchip DisplayPort PHY module. This is required to get DisplayPort working in Rockchip SoCs. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> --- Changes in v12: - Re-order the include headers file alphabetically in phy-rockchip-dp.c (Jingoo) Changes in v11: None Changes in v10: - Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4) -> BIT(20) Changes in v9: - Removed the unused the variable "res" in probe function. (Heiko) - Removed the unused head file. Changes in v8: - Fix the mixed spacers on macro definitions. (Heiko) - Remove the unnecessary empty line after clk_prepare_enable. (Heiko) Changes in v7: - Simply the commit message. (Kishon) - Symmetrical enable/disbale the phy clock and power. (Kishon) Changes in v6: None Changes in v5: - Remove "reg" DT property, cause driver could poweron/poweroff phy via the exist "grf" syscon already. And rename the example DT node from "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko) - Add deivce_node at the front of driver, update phy_ops type from "static struct" to "static const struct". And correct the input paramters of devm_phy_create() interfaces. (Heiko) Changes in v4: - Add commit message, and remove the redundant rockchip_dp_phy_init() function, move those code to probe() method. And remove driver .owner number. (Kishon) Changes in v3: - Suggest, add rockchip dp phy driver, collect the phy clocks and power control. (Heiko) Changes in v2: None drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/phy/phy-rockchip-dp.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 7eb5859d..7355819 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB help Enable this to support the Rockchip USB 2.0 PHY. +config PHY_ROCKCHIP_DP + tristate "Rockchip Display Port PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip Display Port PHY. + config PHY_ST_SPEAR1310_MIPHY tristate "ST SPEAR1310-MIPHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 075db1a..b1700cd 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c new file mode 100644 index 0000000..88f09ec --- /dev/null +++ b/drivers/phy/phy-rockchip-dp.c @@ -0,0 +1,151 @@ +/* + * Rockchip DP PHY driver + * + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd. + * Author: Yakir Yang <ykk@@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + */ + +#include <linux/clk.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define GRF_SOC_CON12 0x0274 + +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20) +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4) + +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21) +#define GRF_EDP_PHY_SIDDQ_ON 0 +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5) + +struct rockchip_dp_phy { + struct device *dev; + struct regmap *grf; + struct clk *phy_24m; +}; + +static int rockchip_set_phy_state(struct phy *phy, bool enable) +{ + struct rockchip_dp_phy *dp = phy_get_drvdata(phy); + int ret; + + if (enable) { + ret = regmap_write(dp->grf, GRF_SOC_CON12, + GRF_EDP_PHY_SIDDQ_HIWORD_MASK | + GRF_EDP_PHY_SIDDQ_ON); + if (ret < 0) { + dev_err(dp->dev, "Can't enable PHY power %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(dp->phy_24m); + } else { + clk_disable_unprepare(dp->phy_24m); + + ret = regmap_write(dp->grf, GRF_SOC_CON12, + GRF_EDP_PHY_SIDDQ_HIWORD_MASK | + GRF_EDP_PHY_SIDDQ_OFF); + } + + return ret; +} + +static int rockchip_dp_phy_power_on(struct phy *phy) +{ + return rockchip_set_phy_state(phy, true); +} + +static int rockchip_dp_phy_power_off(struct phy *phy) +{ + return rockchip_set_phy_state(phy, false); +} + +static const struct phy_ops rockchip_dp_phy_ops = { + .power_on = rockchip_dp_phy_power_on, + .power_off = rockchip_dp_phy_power_off, + .owner = THIS_MODULE, +}; + +static int rockchip_dp_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct phy_provider *phy_provider; + struct rockchip_dp_phy *dp; + struct phy *phy; + int ret; + + if (!np) + return -ENODEV; + + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); + if (IS_ERR(dp)) + return -ENOMEM; + + dp->dev = dev; + + dp->phy_24m = devm_clk_get(dev, "24m"); + if (IS_ERR(dp->phy_24m)) { + dev_err(dev, "cannot get clock 24m\n"); + return PTR_ERR(dp->phy_24m); + } + + ret = clk_set_rate(dp->phy_24m, 24000000); + if (ret < 0) { + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret); + return ret; + } + + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(dp->grf)) { + dev_err(dev, "rk3288-dp needs rockchip,grf property\n"); + return PTR_ERR(dp->grf); + } + + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER | + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK); + if (ret != 0) { + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret); + return ret; + } + + phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy\n"); + return PTR_ERR(phy); + } + phy_set_drvdata(phy, dp); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_dp_phy_dt_ids[] = { + { .compatible = "rockchip,rk3288-dp-phy" }, + {} +}; + +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids); + +static struct platform_driver rockchip_dp_phy_driver = { + .probe = rockchip_dp_phy_probe, + .driver = { + .name = "rockchip-dp-phy", + .of_match_table = rockchip_dp_phy_dt_ids, + }, +}; + +module_platform_driver(rockchip_dp_phy_driver); + +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); +MODULE_DESCRIPTION("Rockchip DP PHY driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1
next prev parent reply other threads:[~2015-12-23 12:38 UTC|newest] Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-12-23 12:25 [PATCH v12 0/18] Add Analogix Core Display Port Driver Yakir Yang 2015-12-23 12:25 ` Yakir Yang 2015-12-23 12:25 ` Yakir Yang 2015-12-23 12:29 ` [PATCH v12 01/18] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang 2015-12-23 12:29 ` Yakir Yang 2015-12-23 12:31 ` [PATCH v12 02/18] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang 2015-12-23 12:31 ` Yakir Yang 2015-12-23 12:31 ` Yakir Yang 2015-12-23 12:31 ` [PATCH v12 03/18] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang 2015-12-23 12:31 ` Yakir Yang 2015-12-23 12:31 ` Yakir Yang 2015-12-23 12:31 ` [PATCH v12 04/18] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang 2015-12-23 12:31 ` Yakir Yang 2015-12-23 12:31 ` Yakir Yang 2015-12-23 12:32 ` [PATCH v12 05/18] dt-bindings: add document for analogix display port driver Yakir Yang 2015-12-23 12:32 ` Yakir Yang 2015-12-23 12:32 ` Yakir Yang 2015-12-23 12:32 ` [PATCH v12 06/18] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang 2015-12-23 12:32 ` Yakir Yang 2015-12-23 12:32 ` Yakir Yang 2015-12-23 12:32 ` [PATCH v12 07/18] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang 2015-12-23 12:32 ` Yakir Yang 2015-12-23 12:34 ` [PATCH v12 08/18] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang 2015-12-23 12:34 ` Yakir Yang 2015-12-23 12:36 ` Yakir Yang [this message] 2015-12-23 12:36 ` [PATCH v12 09/18] phy: Add driver for rockchip Display Port PHY Yakir Yang 2015-12-23 12:38 ` [PATCH v12 10/18] dt-bindings: add document for rockchip dp phy Yakir Yang 2015-12-23 12:38 ` Yakir Yang 2015-12-23 12:40 ` [PATCH v12 11/18] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang 2015-12-23 12:40 ` Yakir Yang 2015-12-23 12:42 ` [PATCH v12 12/18] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang 2015-12-23 12:42 ` Yakir Yang 2015-12-23 12:42 ` Yakir Yang 2015-12-23 12:44 ` [PATCH v12 13/18] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang 2015-12-23 12:44 ` Yakir Yang 2015-12-23 12:46 ` [PATCH v12 14/18] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang 2015-12-23 12:46 ` Yakir Yang 2015-12-23 12:46 ` Yakir Yang 2015-12-23 12:49 ` [PATCH v12 15/18] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang 2015-12-23 12:49 ` Yakir Yang 2015-12-23 12:49 ` Yakir Yang 2015-12-23 12:51 ` [PATCH v12 16/18] drm: bridge: analogix/dp: expand the wait time for looking AUX CH reply flag Yakir Yang 2015-12-23 12:51 ` Yakir Yang 2015-12-23 15:10 ` Jingoo Han 2015-12-23 15:10 ` Jingoo Han 2015-12-23 15:10 ` Jingoo Han 2015-12-24 1:23 ` Yakir Yang 2015-12-24 1:23 ` Yakir Yang 2015-12-24 1:23 ` Yakir Yang 2015-12-25 13:01 ` Jingoo Han 2015-12-25 13:01 ` Jingoo Han 2015-12-25 13:01 ` Jingoo Han 2015-12-23 12:53 ` [PATCH v12 17/18] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time Yakir Yang 2015-12-23 12:53 ` Yakir Yang 2015-12-23 12:55 ` [PATCH v12 18/18] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time Yakir Yang 2015-12-23 12:55 ` Yakir Yang 2015-12-23 12:55 ` Yakir Yang 2016-01-13 14:59 ` [PATCH v12 0/18] Add Analogix Core Display Port Driver Heiko Stuebner 2016-01-13 14:59 ` Heiko Stuebner 2016-01-13 14:59 ` Heiko Stuebner 2016-01-17 14:25 ` Heiko Stuebner 2016-01-17 14:25 ` Heiko Stuebner 2016-01-17 14:25 ` Heiko Stuebner 2016-01-17 14:25 ` Heiko Stuebner 2016-01-18 10:48 ` Yakir Yang 2016-01-18 10:48 ` Yakir Yang 2016-01-18 10:48 ` Yakir Yang 2016-01-19 9:58 ` [PATCH v12.1 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang 2016-01-19 9:58 ` Yakir Yang 2016-01-19 10:00 ` [PATCH v12.1 05/17] dt-bindings: add document for analogix display port driver Yakir Yang 2016-01-19 10:00 ` Yakir Yang 2016-01-19 10:00 ` Yakir Yang 2016-01-19 10:02 ` [PATCH v12.1 06/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang 2016-01-19 10:02 ` Yakir Yang 2016-01-19 10:02 ` Yakir Yang 2016-01-19 10:04 ` [PATCH v12.1 07/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang 2016-01-19 10:04 ` Yakir Yang 2016-01-21 19:11 ` Heiko Stuebner 2016-01-21 19:11 ` Heiko Stuebner 2016-01-22 1:37 ` Yakir Yang 2016-01-22 1:37 ` Yakir Yang 2016-01-22 1:37 ` Yakir Yang 2016-01-19 10:06 ` [PATCH v12.1 13/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang 2016-01-19 10:06 ` Yakir Yang 2016-01-19 10:06 ` Yakir Yang
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