From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>, <marc.zyngier@arm.com>,
<christoffer.dall@linaro.org>
Cc: kvm@vger.kernel.org, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org
Subject: [PATCH v9 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
Date: Fri, 15 Jan 2016 14:27:40 +0800 [thread overview]
Message-ID: <1452839275-19368-7-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1452839275-19368-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index fc60041..06257e2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -492,6 +492,27 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (!kvm_arm_pmu_v3_ready(vcpu))
+ return trap_raz_wi(vcpu, p, r);
+
+ if (p->is_write)
+ return false;
+
+ if (!(p->Op2 & 1))
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ p->regval = pmceid;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -694,10 +715,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmceid },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -943,8 +964,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com,
christoffer.dall@linaro.org
Cc: kvm@vger.kernel.org, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org
Subject: [PATCH v9 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
Date: Fri, 15 Jan 2016 14:27:40 +0800 [thread overview]
Message-ID: <1452839275-19368-7-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1452839275-19368-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index fc60041..06257e2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -492,6 +492,27 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (!kvm_arm_pmu_v3_ready(vcpu))
+ return trap_raz_wi(vcpu, p, r);
+
+ if (p->is_write)
+ return false;
+
+ if (!(p->Op2 & 1))
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ p->regval = pmceid;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -694,10 +715,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmceid },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -943,8 +964,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
Date: Fri, 15 Jan 2016 14:27:40 +0800 [thread overview]
Message-ID: <1452839275-19368-7-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1452839275-19368-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index fc60041..06257e2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -492,6 +492,27 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ u64 pmceid;
+
+ if (!kvm_arm_pmu_v3_ready(vcpu))
+ return trap_raz_wi(vcpu, p, r);
+
+ if (p->is_write)
+ return false;
+
+ if (!(p->Op2 & 1))
+ asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+ else
+ asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+ p->regval = pmceid;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -694,10 +715,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmceid },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmceid },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
trap_raz_wi },
@@ -943,8 +964,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
- { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
--
2.0.4
next prev parent reply other threads:[~2016-01-15 6:27 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-15 6:27 [PATCH v9 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao [this message]
2016-01-15 6:27 ` [PATCH v9 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 11:08 ` Andrew Jones
2016-01-15 11:08 ` Andrew Jones
2016-01-19 7:10 ` Shannon Zhao
2016-01-19 7:10 ` Shannon Zhao
2016-01-25 16:47 ` Peter Maydell
2016-01-25 16:47 ` Peter Maydell
2016-01-26 3:40 ` Shannon Zhao
2016-01-26 3:40 ` Shannon Zhao
2016-01-26 3:40 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 11:16 ` Andrew Jones
2016-01-15 11:16 ` Andrew Jones
2016-01-15 6:27 ` [PATCH v9 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 6:27 ` Shannon Zhao
2016-01-15 13:28 ` Andrew Jones
2016-01-15 13:28 ` Andrew Jones
2016-01-15 13:58 ` Shannon Zhao
2016-01-15 13:58 ` Shannon Zhao
2016-01-25 16:53 ` Peter Maydell
2016-01-25 16:53 ` Peter Maydell
2016-01-26 3:33 ` Shannon Zhao
2016-01-26 3:33 ` Shannon Zhao
2016-01-26 3:33 ` Shannon Zhao
2016-01-15 13:45 ` [PATCH v9 00/21] KVM: ARM64: Add guest PMU support Andrew Jones
2016-01-15 13:45 ` Andrew Jones
2016-01-15 14:04 ` Shannon Zhao
2016-01-15 14:04 ` Shannon Zhao
2016-01-16 7:33 ` Shannon Zhao
2016-01-16 7:33 ` Shannon Zhao
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