From: Shannon Zhao <zhaoshenglong@huawei.com>
To: <kvmarm@lists.cs.columbia.edu>, <marc.zyngier@arm.com>,
<christoffer.dall@linaro.org>
Cc: <linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>,
<will.deacon@arm.com>, <wei@redhat.com>, <cov@codeaurora.org>,
<shannon.zhao@linaro.org>, <peter.huangpeng@huawei.com>,
<hangaohuai@huawei.com>, <zhaoshenglong@huawei.com>
Subject: [PATCH v11 05/21] KVM: ARM64: Add access handler for PMSELR register
Date: Fri, 5 Feb 2016 15:14:00 +0800 [thread overview]
Message-ID: <1454656456-11640-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1454656456-11640-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 97fea84..fc60041 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -477,6 +477,21 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (!kvm_arm_pmu_v3_ready(vcpu))
+ return trap_raz_wi(vcpu, p, r);
+
+ if (p->is_write)
+ vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
+ else
+ /* return PMSELR.SEL field */
+ p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -676,7 +691,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
trap_raz_wi },
@@ -927,7 +942,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com,
christoffer.dall@linaro.org
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
will.deacon@arm.com, wei@redhat.com, cov@codeaurora.org,
shannon.zhao@linaro.org, peter.huangpeng@huawei.com,
hangaohuai@huawei.com, zhaoshenglong@huawei.com
Subject: [PATCH v11 05/21] KVM: ARM64: Add access handler for PMSELR register
Date: Fri, 5 Feb 2016 15:14:00 +0800 [thread overview]
Message-ID: <1454656456-11640-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1454656456-11640-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 97fea84..fc60041 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -477,6 +477,21 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (!kvm_arm_pmu_v3_ready(vcpu))
+ return trap_raz_wi(vcpu, p, r);
+
+ if (p->is_write)
+ vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
+ else
+ /* return PMSELR.SEL field */
+ p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -676,7 +691,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
trap_raz_wi },
@@ -927,7 +942,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
--
2.0.4
WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v11 05/21] KVM: ARM64: Add access handler for PMSELR register
Date: Fri, 5 Feb 2016 15:14:00 +0800 [thread overview]
Message-ID: <1454656456-11640-6-git-send-email-zhaoshenglong@huawei.com> (raw)
In-Reply-To: <1454656456-11640-1-git-send-email-zhaoshenglong@huawei.com>
From: Shannon Zhao <shannon.zhao@linaro.org>
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 97fea84..fc60041 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -477,6 +477,21 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (!kvm_arm_pmu_v3_ready(vcpu))
+ return trap_raz_wi(vcpu, p, r);
+
+ if (p->is_write)
+ vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
+ else
+ /* return PMSELR.SEL field */
+ p->regval = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+
+ return true;
+}
+
/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
#define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */ \
@@ -676,7 +691,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmselr, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
trap_raz_wi },
@@ -927,7 +942,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
- { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+ { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
--
2.0.4
next prev parent reply other threads:[~2016-02-05 7:19 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 7:13 [PATCH v11 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao [this message]
2016-02-05 7:14 ` [PATCH v11 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:09 ` Christoffer Dall
2016-02-08 12:09 ` Christoffer Dall
2016-02-20 13:15 ` Shannon Zhao
2016-02-20 13:15 ` Shannon Zhao
2016-02-20 13:30 ` Peter Maydell
2016-02-20 13:30 ` Peter Maydell
2016-02-20 13:34 ` Shannon Zhao
2016-02-20 13:34 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:26 ` Christoffer Dall
2016-02-08 12:26 ` Christoffer Dall
2016-02-20 13:32 ` Shannon Zhao
2016-02-20 13:32 ` Shannon Zhao
2016-02-22 7:35 ` Shannon Zhao
2016-02-22 7:35 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:29 ` Christoffer Dall
2016-02-08 12:29 ` Christoffer Dall
2016-02-22 7:43 ` Shannon Zhao
2016-02-22 7:43 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:40 ` Christoffer Dall
2016-02-08 12:40 ` Christoffer Dall
2016-02-20 13:38 ` Shannon Zhao
2016-02-20 13:38 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:52 ` Christoffer Dall
2016-02-08 12:52 ` Christoffer Dall
2016-02-22 7:45 ` Shannon Zhao
2016-02-22 7:45 ` Shannon Zhao
2016-02-22 7:45 ` Shannon Zhao
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