From: Christoffer Dall <christoffer.dall@linaro.org>
To: Shannon Zhao <zhaoshenglong@huawei.com>
Cc: kvmarm@lists.cs.columbia.edu, marc.zyngier@arm.com,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
will.deacon@arm.com, wei@redhat.com, cov@codeaurora.org,
shannon.zhao@linaro.org, peter.huangpeng@huawei.com,
hangaohuai@huawei.com
Subject: Re: [PATCH v11 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
Date: Mon, 8 Feb 2016 13:09:50 +0100 [thread overview]
Message-ID: <20160208120950.GC620@cbox> (raw)
In-Reply-To: <1454656456-11640-7-git-send-email-zhaoshenglong@huawei.com>
On Fri, Feb 05, 2016 at 03:14:01PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add access handler which gets host value of PMCEID0 or PMCEID1 when
> guest access these registers. Writing action to PMCEID0 or PMCEID1 is
> UNDEFINED.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++----
> 1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index fc60041..06257e2 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -492,6 +492,27 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> return true;
> }
>
> +static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> + const struct sys_reg_desc *r)
> +{
> + u64 pmceid;
> +
> + if (!kvm_arm_pmu_v3_ready(vcpu))
> + return trap_raz_wi(vcpu, p, r);
> +
> + if (p->is_write)
> + return false;
Isn't it really a BUG_ON(p->is_write) ?
Presumably a guest write to these registers will raise an undefined
exception in EL0/1 and we don't get here by any other path than the trap
handler, do we?
Otherwise looks good to me.
Thanks,
-Christoffer
WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v11 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register
Date: Mon, 8 Feb 2016 13:09:50 +0100 [thread overview]
Message-ID: <20160208120950.GC620@cbox> (raw)
In-Reply-To: <1454656456-11640-7-git-send-email-zhaoshenglong@huawei.com>
On Fri, Feb 05, 2016 at 03:14:01PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add access handler which gets host value of PMCEID0 or PMCEID1 when
> guest access these registers. Writing action to PMCEID0 or PMCEID1 is
> UNDEFINED.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> arch/arm64/kvm/sys_regs.c | 29 +++++++++++++++++++++++++----
> 1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index fc60041..06257e2 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -492,6 +492,27 @@ static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> return true;
> }
>
> +static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> + const struct sys_reg_desc *r)
> +{
> + u64 pmceid;
> +
> + if (!kvm_arm_pmu_v3_ready(vcpu))
> + return trap_raz_wi(vcpu, p, r);
> +
> + if (p->is_write)
> + return false;
Isn't it really a BUG_ON(p->is_write) ?
Presumably a guest write to these registers will raise an undefined
exception in EL0/1 and we don't get here by any other path than the trap
handler, do we?
Otherwise looks good to me.
Thanks,
-Christoffer
next prev parent reply other threads:[~2016-02-08 12:09 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 7:13 [PATCH v11 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:13 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:09 ` Christoffer Dall [this message]
2016-02-08 12:09 ` Christoffer Dall
2016-02-20 13:15 ` Shannon Zhao
2016-02-20 13:15 ` Shannon Zhao
2016-02-20 13:30 ` Peter Maydell
2016-02-20 13:30 ` Peter Maydell
2016-02-20 13:34 ` Shannon Zhao
2016-02-20 13:34 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:26 ` Christoffer Dall
2016-02-08 12:26 ` Christoffer Dall
2016-02-20 13:32 ` Shannon Zhao
2016-02-20 13:32 ` Shannon Zhao
2016-02-22 7:35 ` Shannon Zhao
2016-02-22 7:35 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:29 ` Christoffer Dall
2016-02-08 12:29 ` Christoffer Dall
2016-02-22 7:43 ` Shannon Zhao
2016-02-22 7:43 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:40 ` Christoffer Dall
2016-02-08 12:40 ` Christoffer Dall
2016-02-20 13:38 ` Shannon Zhao
2016-02-20 13:38 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-05 7:14 ` Shannon Zhao
2016-02-08 12:52 ` Christoffer Dall
2016-02-08 12:52 ` Christoffer Dall
2016-02-22 7:45 ` Shannon Zhao
2016-02-22 7:45 ` Shannon Zhao
2016-02-22 7:45 ` Shannon Zhao
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