From: Xing Zheng <zhengxing@rock-chips.com>
To: heiko@sntech.de
Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org,
briannorris@chromium.org, huangtao@rock-chips.com,
zhangqing@rock-chips.com, Xing Zheng <zhengxing@rock-chips.com>,
devicetree@vger.kernel.org, Jianqun Xu <jay.xu@rock-chips.com>,
frank.wang@rock-chips.com, shawn.lin@rock-chips.com,
Michael Turquette <mturquette@baylibre.com>,
Kumar Gala <galak@codeaurora.org>,
linux-kernel@vger.kernel.org,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
wulf@rock-chips.com, Mark Rutland <mark.rutland@arm.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom
Date: Mon, 1 Aug 2016 12:23:03 +0800 [thread overview]
Message-ID: <1470025389-4094-1-git-send-email-zhengxing@rock-chips.com> (raw)
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
clk: rockchip: rk3399: Add support frac mode frequencies
drivers/clk/rockchip/clk-rk3399.c | 35 +++++++++++++++++++++++++-------
include/dt-bindings/clock/rk3399-cru.h | 2 ++
2 files changed, 30 insertions(+), 7 deletions(-)
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org
Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Jianqun Xu <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: [RESEND PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom
Date: Mon, 1 Aug 2016 12:23:03 +0800 [thread overview]
Message-ID: <1470025389-4094-1-git-send-email-zhengxing@rock-chips.com> (raw)
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
clk: rockchip: rk3399: Add support frac mode frequencies
drivers/clk/rockchip/clk-rk3399.c | 35 +++++++++++++++++++++++++-------
include/dt-bindings/clock/rk3399-cru.h | 2 ++
2 files changed, 30 insertions(+), 7 deletions(-)
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: zhengxing@rock-chips.com (Xing Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom
Date: Mon, 1 Aug 2016 12:23:03 +0800 [thread overview]
Message-ID: <1470025389-4094-1-git-send-email-zhengxing@rock-chips.com> (raw)
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (5):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
clk: rockchip: rk3399: Add support frac mode frequencies
drivers/clk/rockchip/clk-rk3399.c | 35 +++++++++++++++++++++++++-------
include/dt-bindings/clock/rk3399-cru.h | 2 ++
2 files changed, 30 insertions(+), 7 deletions(-)
--
1.7.9.5
next reply other threads:[~2016-08-01 4:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-01 4:23 Xing Zheng [this message]
2016-08-01 4:23 ` [RESEND PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng
2016-08-01 4:23 ` Xing Zheng
2016-08-01 4:23 ` [RESEND PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng
2016-08-01 4:23 ` Xing Zheng
2016-08-01 4:23 ` [RESEND PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng
2016-08-01 4:23 ` Xing Zheng
2016-08-01 4:23 ` [RESEND PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng
2016-08-01 4:23 ` Xing Zheng
2016-08-01 4:23 ` [RESEND PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng
2016-08-01 4:23 ` Xing Zheng
2016-08-01 4:24 ` [RESEND PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng
2016-08-01 4:24 ` Xing Zheng
2016-08-01 8:47 ` Shawn Lin
2016-08-01 8:47 ` Shawn Lin
2016-08-01 8:47 ` Shawn Lin
2016-08-01 4:25 ` [RESEND PATCH 6/6] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng
2016-08-01 4:25 ` Xing Zheng
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