[RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup

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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Cc: <nsekhar@ti.com>, <kishon@ti.com>
Subject: [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Thu, 9 Mar 2017 12:08:59 +0530	[thread overview]
Message-ID: <1489041545-15730-2-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1489041545-15730-1-git-send-email-kishon@ti.com>

Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.

Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-designware.c |    3 +++
 drivers/pci/dwc/pcie-designware.h |    1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d..14ee7a3 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 {
 	u32 retries, val;
 
+	if (pp->ops->cpu_addr_fixup)
+		cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
+
 	if (pci->iatu_unroll_enabled) {
 		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 				      lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b871..8f3dcb2 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
+	u64	(*cpu_addr_fixup)(u64 cpu_addr);
 	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
 	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)

From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Cc: nsekhar@ti.com, kishon@ti.com
Subject: [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Thu, 9 Mar 2017 12:08:59 +0530	[thread overview]
Message-ID: <1489041545-15730-2-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1489041545-15730-1-git-send-email-kishon@ti.com>

Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.

Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-designware.c |    3 +++
 drivers/pci/dwc/pcie-designware.h |    1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d..14ee7a3 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 {
 	u32 retries, val;
 
+	if (pp->ops->cpu_addr_fixup)
+		cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
+
 	if (pci->iatu_unroll_enabled) {
 		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 				      lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b871..8f3dcb2 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
+	u64	(*cpu_addr_fixup)(u64 cpu_addr);
 	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
 	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
-- 
1.7.9.5


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)

From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: nsekhar@ti.com, kishon@ti.com
Subject: [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Thu, 9 Mar 2017 12:08:59 +0530	[thread overview]
Message-ID: <1489041545-15730-2-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1489041545-15730-1-git-send-email-kishon@ti.com>

Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.

Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-designware.c |    3 +++
 drivers/pci/dwc/pcie-designware.h |    1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d..14ee7a3 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 {
 	u32 retries, val;
 
+	if (pp->ops->cpu_addr_fixup)
+		cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
+
 	if (pci->iatu_unroll_enabled) {
 		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 				      lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b871..8f3dcb2 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
+	u64	(*cpu_addr_fixup)(u64 cpu_addr);
 	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
 	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
-- 
1.7.9.5

WARNING: multiple messages have this Message-ID (diff)

From: kishon@ti.com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup
Date: Thu, 9 Mar 2017 12:08:59 +0530	[thread overview]
Message-ID: <1489041545-15730-2-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1489041545-15730-1-git-send-email-kishon@ti.com>

Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.

Acked-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/dwc/pcie-designware.c |    3 +++
 drivers/pci/dwc/pcie-designware.h |    1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 7e1fb7d..14ee7a3 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
 {
 	u32 retries, val;
 
+	if (pp->ops->cpu_addr_fixup)
+		cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
+
 	if (pci->iatu_unroll_enabled) {
 		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 				      lower_32_bits(cpu_addr));
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index cd3b871..8f3dcb2 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -143,6 +143,7 @@ struct pcie_port {
 };
 
 struct dw_pcie_ops {
+	u64	(*cpu_addr_fixup)(u64 cpu_addr);
 	u32	(*readl_dbi)(struct dw_pcie *pcie, u32 reg);
 	void	(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
 	int	(*link_up)(struct dw_pcie *pcie);
-- 
1.7.9.5

next prev parent reply	other threads:[~2017-03-09  6:40 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-09  6:38 [RESEND PATCH v3 0/7] PCI: dwc: Miscellaneous fixes and cleanups Kishon Vijay Abraham I
2017-03-09  6:38 ` Kishon Vijay Abraham I
2017-03-09  6:38 ` Kishon Vijay Abraham I
2017-03-09  6:38 ` Kishon Vijay Abraham I
2017-03-09  6:38 ` Kishon Vijay Abraham I [this message]
2017-03-09  6:38   ` [RESEND PATCH v3 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Kishon Vijay Abraham I
2017-03-09  6:38   ` Kishon Vijay Abraham I
2017-03-09  6:38   ` Kishon Vijay Abraham I
2017-03-09  6:39 ` [RESEND PATCH v3 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39 ` [RESEND PATCH v3 3/7] PCI: dwc: artpec6: " Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09 10:21   ` Niklas Cassel
2017-03-09 10:21     ` Niklas Cassel
2017-03-09 10:21     ` Niklas Cassel
2017-03-09 10:21     ` Niklas Cassel
2017-03-09  6:39 ` [RESEND PATCH v3 4/7] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09 14:48   ` Niklas Cassel
2017-03-09 14:48     ` Niklas Cassel
2017-03-09 14:48     ` Niklas Cassel
2017-03-09 14:48     ` Niklas Cassel
2017-03-09 15:05     ` Niklas Cassel
2017-03-09 15:05       ` Niklas Cassel
2017-03-09 15:05       ` Niklas Cassel
2017-03-09 15:05       ` Niklas Cassel
2017-03-10 11:36       ` Kishon Vijay Abraham I
2017-03-10 11:36         ` Kishon Vijay Abraham I
2017-03-10 11:36         ` Kishon Vijay Abraham I
2017-03-10 11:36         ` Kishon Vijay Abraham I
2017-03-10 12:23         ` Niklas Cassel
2017-03-10 12:23           ` Niklas Cassel
2017-03-10 12:23           ` Niklas Cassel
2017-03-10 12:23           ` Niklas Cassel
2017-03-10 12:30         ` Joao Pinto
2017-03-10 12:30           ` Joao Pinto
2017-03-10 12:30           ` Joao Pinto
2017-03-10 12:30           ` Joao Pinto
2017-03-10 12:31         ` Niklas Cassel
2017-03-10 12:31           ` Niklas Cassel
2017-03-10 12:31           ` Niklas Cassel
2017-03-10 12:31           ` Niklas Cassel
2017-03-10 12:56           ` Kishon Vijay Abraham I
2017-03-10 12:56             ` Kishon Vijay Abraham I
2017-03-10 12:56             ` Kishon Vijay Abraham I
2017-03-10 12:56             ` Kishon Vijay Abraham I
2017-03-10 15:47             ` Niklas Cassel
2017-03-10 15:47               ` Niklas Cassel
2017-03-10 15:47               ` Niklas Cassel
2017-03-10 15:47               ` Niklas Cassel
2017-03-13  5:30               ` Kishon Vijay Abraham I
2017-03-13  5:30                 ` Kishon Vijay Abraham I
2017-03-13  5:30                 ` Kishon Vijay Abraham I
2017-03-13  5:30                 ` Kishon Vijay Abraham I
2017-03-09  6:39 ` [RESEND PATCH v3 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09 14:48   ` Niklas Cassel
2017-03-09 14:48     ` Niklas Cassel
2017-03-09 14:48     ` Niklas Cassel
2017-03-09 14:48     ` Niklas Cassel
2017-03-10 12:04     ` Kishon Vijay Abraham I
2017-03-10 12:04       ` Kishon Vijay Abraham I
2017-03-10 12:04       ` Kishon Vijay Abraham I
2017-03-10 12:04       ` Kishon Vijay Abraham I
2017-03-10 12:56       ` Niklas Cassel
2017-03-10 12:56         ` Niklas Cassel
2017-03-10 12:56         ` Niklas Cassel
2017-03-10 12:56         ` Niklas Cassel
2017-03-10 13:04         ` Kishon Vijay Abraham I
2017-03-10 13:04           ` Kishon Vijay Abraham I
2017-03-10 13:04           ` Kishon Vijay Abraham I
2017-03-10 13:04           ` Kishon Vijay Abraham I
2017-03-10 14:59           ` Niklas Cassel
2017-03-10 14:59             ` Niklas Cassel
2017-03-10 14:59             ` Niklas Cassel
2017-03-10 14:59             ` Niklas Cassel
2017-03-09  6:39 ` [RESEND PATCH v3 6/7] PCI: dwc: designware: Move _unroll configurations to a separate function Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09 12:25   ` Joao Pinto
2017-03-09 12:25     ` Joao Pinto
2017-03-09 12:25     ` Joao Pinto
2017-03-09 12:25     ` Joao Pinto
2017-03-09  6:39 ` [RESEND PATCH v3 7/7] PCI: dwc: dra7xx: Push request_irq call to the bottom of probe Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I
2017-03-09  6:39   ` Kishon Vijay Abraham I

find likely ancestor, descendant, or conflicting patches for this message:
dfblob:7e1fb7d dfblob:cd3b871 dfblob:7e1fb7d dfblob:cd3b871
dfblob:7e1fb7d dfblob:cd3b871 dfblob:7e1fb7d dfblob:cd3b871
dfblob:14ee7a3 dfblob:8f3dcb2 dfblob:14ee7a3 dfblob:8f3dcb2
dfblob:14ee7a3 dfblob:8f3dcb2 dfblob:14ee7a3 dfblob:8f3dcb2
	(help)

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